forked from opendacs/PyHCL
35 lines
725 B
Python
35 lines
725 B
Python
# Copyright (c) 2019 scutdig
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# Licensed under the MIT license.
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from pyhcl import *
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class Add(BlackBox):
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io = IO(
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in1=Input(U.w(32)),
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in2=Input(U.w(32)),
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out=Output(U.w(32)),
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)
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class M(Module):
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io = IO(
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i=Input(U.w(32)),
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o=Output(U.w(32)),
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)
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bbox = Add()
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bbox.io.in1 @= io.i
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bbox.io.in2 @= io.i
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io.o @= bbox.io.out
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fircode = """module Add :
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input in1 : UInt<32>
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input in2 : UInt<32>
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output out : UInt<32>
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out <= add(in1, in2)
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"""
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addfirrtlmodule(Add, fircode)
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if __name__ == '__main__':
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#Emitter.dumpVerilog(Emitter.dump(Emitter.emit(M()), "Top.fir"))
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from pyhcl.simulator import Simlite
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s = Simlite(M(), dpiconfig=None) |