forked from opendacs/PyHCL
94 lines
1.8 KiB
Markdown
94 lines
1.8 KiB
Markdown
# Structuring
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## module and hierarchy
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* All circle must extends `Module`
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```python
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class FullAdder(Module):
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io = IO(
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a=Input(Bool),
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b=Input(Bool),
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cin=Input(Bool),
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sum=Output(Bool),
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cout=Output(Bool),
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)
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# Generate the sum
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a_xor_b = io.a ^ io.b
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io.sum @= a_xor_b ^ io.cin
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# Generate the carry
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a_and_b = io.a & io.b
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b_and_cin = io.b & io.cin
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a_and_cin = io.a & io.cin
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io.cout @= a_and_b | b_and_cin | a_and_cin
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```
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## Clock domains
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```python
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class Counter(RawModule):
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io = IO(
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i=Input(Bool),
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o=Output(U.w(32)),
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)
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myclk = Clock()
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myrst = Reset()
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with clockdomin(myclk, myrst):
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r0 = RegInit(U.w(32)(0))
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with when(io.i):
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r0 @= r0 + U.w(32)(1)
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io.o @= r0
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```
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## Instamtiate Verilog IP
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```python
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class BBox(BlackBox):
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io = IO(
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in1=Input(U.w(64)),
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in2=Input(U.w(64)),
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out=Output(U.w(64)),
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)
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class M(Module):
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io = IO(
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i = Input(U.w(64)),
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o = Output(U.w(64)),
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)
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bbox = BBox()
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bbox.io.in1 @= io.i
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bbox.io.in2 @= io.i
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io.o @= bbox.io.out
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if __name__ == '__main__':
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Emitter.dumpVerilog(Emitter.dump(Emitter.emit(M()), "bbox.fir"))
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```
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## Parametrization
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```python
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def myManyDynamicElementVecFir(length: int, consts: List):
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class MyManyDynamicElementVecFir(Module):
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io = IO(
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i=Input(U.w(8)),
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valid=Input(Bool),
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o=Output(U.w(8)),
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)
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taps = [io.i] + [RegInit(U.w(8)(0)) for _ in range(length)]
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for a, b in zip(taps, taps[1:]):
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with when(io.valid):
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b @= a
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m = map(lambda x: x[0] * x[1], zip(taps, consts))
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io.o @= reduce(lambda x, y: x + y, m)
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return MyManyDynamicElementVecFir()
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``` |