forked from opendacs/PyHCL
38 lines
1.1 KiB
Markdown
38 lines
1.1 KiB
Markdown
---
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sort: 12
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---
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# Examples
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## Introduction
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Examples are split into three kinds:
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- Simple examples that could be used to get used to the basics of PyHCL.
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- Intermediate examples which implement components by using a traditional approach.
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- Advanced examples which go further than traditional HDL by using object-oriented programming, functional programming, and meta-hardware description.
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They are all accessible in the sidebar under the corresponding sections.
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## Getting started
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All examples assume that you have the following imports on the top of your scala file:
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```python
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from pyhcl import *
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```
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To generate `Verilog`, `highFirrtl`, `lowFirrtl` for a given Module, you can place the following at the bottom of your python file:
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```python
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if __name__ == '__main__':
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# emit high firrtl
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Emitter.dump(Emitter.emit(FullAdder(), HighForm), "FullAdder.fir")
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# emit lowered firrtl
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Emitter.dump(Emitter.emit(FullAdder(), LowForm), "FullAdder.lo.fir")
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# emit verilog
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Emitter.dump(Emitter.emit(FullAdder(), Verilog), "FullAdder.v")
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```
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{% include list.liquid %} |