update

main.py

@@ -8,9 +8,11 @@
 # from injector import simlite_v2
 # from injector import simlite_v4
 
-# from myTests import test_simlite_1
-from myTests import test_simlite_2
-from myTests import test_verilog_1
+# from myTests import test_simlite
+# from myTests import test_simlite_pysv
+# from myTests import test_simlite_fork
+# from myTests import test_verilog
+from myTests import test_verilog_fork
 
 
 # class MOD(Module):
@@ -46,9 +48,12 @@ def main():
     # simlite_2.main()
     # Simlite_task.test()
 
-    # test_simlite_1.main()
-    test_simlite_2.main()
-    # test_verilog_1.main()
+    # test_simlite.main()
+    # test_simlite_pysv.main()
+    # test_simlite_fork.main()
+
+    # test_verilog.main()
+    test_verilog_fork.main()
     pass
 
 

myTests/test_simlite_fork.py

@@ -0,0 +1,75 @@
+from pyhcl import *
+from pyhcl.simulator import Simlite
+import random
+
+
+class Top(Module):
+    io = IO(
+        a=Input(U.w(32)),
+        b=Input(U.w(32)),
+        c=Output(U.w(32))
+    )
+
+    io.c <<= io.a + io.b
+
+
+# 每次给输入端口赋值, 跑一个时间单位
+def test_step(s):
+    s.start()
+
+    s.step([20, 20])
+    print("cnt: %d\t\tresult:%s" % (s.cnt, s.getRes()))
+    s.step([15, 10])
+    print("cnt: %d\t\tresult:%s" % (s.cnt, s.getRes()))
+    s.step([1000, 1])
+    print("cnt: %d\t\tresult:%s" % (s.cnt, s.getRes()))
+    s.step([999, 201])
+    print("cnt: %d\t\tresult:%s" % (s.cnt, s.getRes()))
+
+    s.stop()
+
+
+def test_task(s):
+    tasks = []
+    tasks.append([20, 20])
+    tasks.append([15, 10])
+    tasks.append([1000, 1])
+    tasks.append([999, 201])
+
+    s.start_task('Top', tasks)
+
+
+def randomInput(ifn):
+    fd = open(ifn, "w")
+    instr = ""
+    for i in range(100):
+        instr += "0 " + str(random.randint(1, 2000)) + ' ' + str(random.randint(1, 2000)) + "\n"
+    instr = instr + "-1\n"
+    fd.write(instr)
+    fd.close()
+
+
+def test_file(s, num):
+    ifn = f"../myTests/tmp/Top_inputs" + str(num)
+    ofn = f"../myTests/tmp/Top_outputs" + str(num)
+    randomInput(ifn)
+    s.start(mode="task", ofn=ofn, ifn=ifn)
+    pass
+
+
+def main():
+    # Emitter.dumpVerilog(Emitter.dump(Emitter.emit(Top()), "Top.fir"))
+    s1 = Simlite(Top(), debug=True)
+    s2 = Simlite(s1)
+
+    # test_step(s)
+    # test_task(s)
+    test_file(s1, 1)
+    test_file(s2, 2)
+
+    s1.close()
+    s2.close()
+
+
+if __name__ == '__main__':
+    main()

myTests/test_verilog_fork.py

@@ -0,0 +1,62 @@
+from pyhcl.simulator.simlite_verilog import Simlite
+import random
+
+
+# 每次给输入端口赋值, 跑一个时间单位
+def test_step(s):
+    s.start()
+    s.step([0, 0, 20, 20])
+    print("cnt: %d\t\tresult:%s" % (s.cnt, s.getRes()))
+    s.step([1, 0, 15, 10])
+    print("cnt: %d\t\tresult:%s" % (s.cnt, s.getRes()))
+    s.step([0, 0, 1000, 1])
+    print("cnt: %d\t\tresult:%s" % (s.cnt, s.getRes()))
+    s.step([1, 0, 999, 201])
+    print("cnt: %d\t\tresult:%s" % (s.cnt, s.getRes()))
+    s.stop()
+
+
+def test_task(s):
+    tasks = []
+    tasks.append([0, 0, 20, 20])
+    tasks.append([1, 0, 15, 10])
+    tasks.append([0, 0, 1000, 1])
+    tasks.append([1, 0, 999, 201])
+
+    s.start_task('Top', tasks)
+
+
+def randomInput(ifn):
+    fd = open(ifn, "w")
+    instr = ""
+    for i in range(100):
+        instr += "0 0 0 " + str(random.randint(1, 2000)) + ' ' + str(random.randint(1, 2000)) + "\n"
+    instr = instr + "-1\n"
+    fd.write(instr)
+    fd.close()
+
+
+def test_file(s, num):
+    ifn = f"../myTests/tmp/Top_inputs" + str(num)
+    ofn = f"../myTests/tmp/Top_outputs" + str(num)
+    randomInput(ifn)
+    s.start(mode="task", ofn=ofn, ifn=ifn)
+    pass
+
+
+def main():
+    top_module_name = 'Top.v'
+    dut_path = 'myTests/tmp/dut/'
+    s1 = Simlite(top_module_name, dut_path, debug=True)
+    s2 = Simlite(module=s1)
+
+    test_file(s1, 1)
+    test_file(s2, 2)
+
+    s1.close()
+    s2.close()
+
+
+if __name__ == '__main__':
+    main()
+    # randomInput(f"../myTests/tmp/Top_inputs")

myTests/test_verilog_pysv.py

@@ -0,0 +1,73 @@
+from pyhcl import *
+from pyhcl.simulator.simlite_verilog import Simlite
+from pysv import sv, DataType, Reference
+import random
+
+
+@sv(a=DataType.UInt, b=DataType.UInt, return_type=Reference(x=DataType.UInt))
+def fn(a, b):
+    return a + b
+
+
+# addpysvmodule(Add, fn)      # 黑盒与函数     # 转换得到.sv/bbox/Add.sv，（SV里调用python函数）
+compile_and_binding_all()   # 编译得到共享库 到.build文件夹下, 生成 SV binding文件 （.sv/pkg/pysv_pkg.sv）
+
+
+# 每次给输入端口赋值, 跑一个时间单位
+def test_step(s):
+    s.start()
+    s.step([0, 0, 20, 20])
+    print("cnt: %d\t\tresult:%s" % (s.cnt, s.getRes()))
+    s.step([1, 0, 15, 10])
+    print("cnt: %d\t\tresult:%s" % (s.cnt, s.getRes()))
+    s.step([0, 0, 1000, 1])
+    print("cnt: %d\t\tresult:%s" % (s.cnt, s.getRes()))
+    s.step([1, 0, 999, 201])
+    print("cnt: %d\t\tresult:%s" % (s.cnt, s.getRes()))
+    s.stop()
+
+
+def test_task(s):
+    tasks = []
+    tasks.append([0, 0, 20, 20])
+    tasks.append([1, 0, 15, 10])
+    tasks.append([0, 0, 1000, 1])
+    tasks.append([1, 0, 999, 201])
+
+    s.start_task('Top', tasks)
+
+
+def randomInput(ifn):
+    fd = open(ifn, "w")
+    instr = ""
+    for i in range(100):
+        instr += "0 0 0 " + str(random.randint(1, 2000)) + ' ' + str(random.randint(1, 2000)) + "\n"
+    instr = instr + "-1\n"
+    fd.write(instr)
+    fd.close()
+
+
+def test_file(s):
+    ifn = f"../myTests/tmp/Top_inputs"
+    ofn = f"../myTests/tmp/Top_outputs"
+    randomInput(ifn)
+    s.start(mode="task", ofn=ofn, ifn=ifn)
+    pass
+
+
+def main():
+    # Emitter.dumpVerilog(Emitter.dump(Emitter.emit(Top()), "Top.fir"))
+    top_module_name = 'Top.v'
+    dut_path = 'myTests/tmp/dut/'
+    s = Simlite(top_module_name, dut_path, debug=True)
+
+    # test_step(s)
+    # test_task(s)
+    test_file(s)
+
+    s.close()
+
+
+if __name__ == '__main__':
+    main()
+    # randomInput(f"../myTests/tmp/Top_inputs")

pyhcl/simulator/simlite_verilog.py

@@ -17,9 +17,10 @@ class Simlite(object):
     # 根据传入的Simlite对象实例，深度复制得到新的Simlite对象实例
     def __fork_init(self, other):
         import copy
+        self.top_module_name = other.top_module_name
         self.dut_path = other.dut_path
         self.dpiconfig = other.dpiconfig
-        if (hasattr(other, "efn")):
+        if hasattr(other, "efn"):
             self.efn = other.efn
         self.inputs = copy.deepcopy(other.inputs)
         self.outputs = copy.deepcopy(other.outputs)