docs init

docs/.debug.yml

@@ -0,0 +1,3 @@
+remote_theme: false
+
+theme: jekyll-rtd-theme

docs/AboutPyHCL/AboutPyHCL.md

@@ -0,0 +1,110 @@
+# PyHCL
+[![Build Status](https://travis-ci.com/scutdig/py-hcl.svg?branch=master)](https://travis-ci.com/scutdig/py-hcl)
+[![codecov](https://codecov.io/gh/scutdig/py-hcl/branch/master/graph/badge.svg)](https://codecov.io/gh/scutdig/py-hcl)
+[![PyPI](https://img.shields.io/pypi/v/py-hcl.svg)](https://pypi.python.org/pypi)
+
+PyHCL is a hardware construct language like [Chisel](https://github.com/freechipsproject/chisel3) but more lightweight and more relaxed to use.
+As a novel hardware construction framework embedded in Python, PyHCL supports several useful features include object-oriented, functional programming,
+and dynamically typed objects.
+
+The goal of PyHCL is providing a complete design and verification tool flow for heterogeneous computing systems flexibly using the same design methodology.
+
+PyHCL is powered by [FIRRTL](https://github.com/freechipsproject/firrtl), an intermediate representation for digital circuit design. With the FIRRTL 
+compiler framework, PyHCL-generated circuits can be compiled to the widely-used HDL Verilog.  
+
+
+## Getting Started
+
+#### Writing A Full Adder
+PyHCL defines modules using only simple Python syntax that looks like this:
+```python
+from pyhcl import *
+
+class FullAdder(Module):
+    io = IO(
+        a=Input(Bool),
+        b=Input(Bool),
+        cin=Input(Bool),
+        sum=Output(Bool),
+        cout=Output(Bool),
+    )
+
+    # Generate the sum
+    io.sum <<= io.a ^ io.b ^ io.cin
+
+    # Generate the carry
+    io.cout <<= io.a & io.b | io.b & io.cin | io.a & io.cin
+```
+
+#### Compiling To FIRRTL
+
+Compiling module by calling `compile_to_firrtl`:
+```python
+Emitter.dump(Emitter.emit(FullAdder()), "FullAdder.fir")
+```
+
+Will generate the following FIRRTL codes:
+```
+circuit FullAdder :
+  module FullAdder :
+    input clock : Clock
+    input reset : UInt<1>
+    input FullAdder_io_a : UInt<1>
+    input FullAdder_io_b : UInt<1>
+    input FullAdder_io_cin : UInt<1>
+    output FullAdder_io_sum : UInt<1>
+    output FullAdder_io_cout : UInt<1>
+
+    node _T_0 = xor(FullAdder_io_a, FullAdder_io_b)
+    node _T_1 = xor(_T_0, FullAdder_io_cin)
+    FullAdder_io_sum <= _T_1
+    node _T_2 = and(FullAdder_io_a, FullAdder_io_b)
+    node _T_3 = and(FullAdder_io_b, FullAdder_io_cin)
+    node _T_4 = or(_T_2, _T_3)
+    node _T_5 = and(FullAdder_io_a, FullAdder_io_cin)
+    node _T_6 = or(_T_4, _T_5)
+    FullAdder_io_cout <= _T_6
+```
+
+#### Compiling To Verilog
+
+While FIRRTL is generated, PyHCL's job is complete. To further compile to Verilog, the [FIRRTL compiler framework](
+https://github.com/freechipsproject/firrtl) is required:
+
+```shell script
+Emitter.dumpVerilog(Emitter.dump(Emitter.emit(FullAdder()), "FullAdder.fir"))
+```
+
+Then `FullAdder.v` will be generated:
+```verilog
+module FullAdder(
+  input   clock,
+  input   reset,
+  input   FullAdder_io_a,
+  input   FullAdder_io_b,
+  input   FullAdder_io_cin,
+  output  FullAdder_io_sum,
+  output  FullAdder_io_cout
+);
+  wire  _T_0;
+  wire  _T_2;
+  wire  _T_3;
+  wire  _T_4;
+  wire  _T_5;
+  assign _T_0 = FullAdder_io_a ^ FullAdder_io_b;
+  assign _T_2 = FullAdder_io_a & FullAdder_io_b;
+  assign _T_3 = FullAdder_io_b & FullAdder_io_cin;
+  assign _T_4 = _T_2 | _T_3;
+  assign _T_5 = FullAdder_io_a & FullAdder_io_cin;
+  assign FullAdder_io_sum = _T_0 ^ FullAdder_io_cin;
+  assign FullAdder_io_cout = _T_4 | _T_5;
+endmodule
+```
+
+
+## Features
+
+- Supports multiple data types: `UInt`, `SInt`, `Vector`, `Bundle`, `Clock`, `Memory`, and casual combination between them.
+- Supports object-oriented inheritance, can compose modules by writing fewer codes.
+- Supports a bunch of convenient operations, such as the addition of `UInt`s, `SInt`s, `Vector`s and `Bundle`s.
+- Supports the parameterization of variables, such as bit width, with the syntax facilities of the host language Python.

docs/AboutPyHCL/readme.md

@@ -0,0 +1,7 @@
+---
+sort: 1
+---
+
+# About Pyhcl
+
+{% include list.liquid %}

docs/Datatypes/Data types.md

@@ -0,0 +1,170 @@
+# Data Types
+
+- Supports multiple data types: `UInt`, `SInt`, `Vector`, `Bundle`, `Clock`, `Memory`, and casual combination between them.
+- Supports object-oriented inheritance, can compose modules by writing fewer codes.
+- Supports a bunch of convenient operations, such as the addition of `UInt`s, `SInt`s, `Vector`s and `Bundle`s.
+- Supports the parameterization of variables, such as bit width, with the syntax facilities of the host language Python.
+
+## Bool
+
+## UInt/SInt
+
+## Bundle
+
+## Vec
+
+
+## Bit
+* `Bool`: bool value
+* `true, false`: boolean literals
+
+## Bits and Integers
+* `U(N.w)`: length `N` unsigned integer that includes Bits operators and
+  unsigned arithmetic (e.g. `+`, `-`, ...) and comparison operators (e.g.
+  `<`, `<=`, ...)
+* `S(N.w)`: length `N` signed integer that includes Bits operators and
+  signed arithmetic (e.g. `+`, `-`, ...) and comparison operators (e.g.
+  `<`, `<=`, ...)
+
+## Vector
+* `Vec(4, U.w(32))`: fixed length array of length `4` containing values of type
+  `U.w(32)` with equality operator (`==`) defined
+
+
+# Type qualifiers
+`Input(T)`, `Output(T)` qualify type `T` to be an input, output, and
+respectively.
+
+# Registers
+Retain state until updated:
+```python
+reg = Reg(U.w(32))
+counter = RegInit(U.w(32)(0))
+```
+
+# Memories
+```python
+m = Mem(10, U.w(8))
+m[U(2)] <<= io.i
+io.o <<= m[U(2)]
+```
+
+# Circuits
+**Defining**:  `Module`
+```python
+from pyhcl import *
+from pyhcl.simulator import Simulator
+
+class FullAdder(Module):
+    io = IO(
+        a=Input(Bool),
+        b=Input(Bool),
+        cin=Input(Bool),
+        sum=Output(Bool),
+        cout=Output(Bool),
+    )
+
+    # Generate the sum
+    a_xor_b = io.a ^ io.b
+    io.sum <<= a_xor_b ^ io.cin
+
+    # Generate the carry
+    a_and_b = io.a & io.b
+    b_and_cin = io.b & io.cin
+    a_and_cin = io.a & io.cin
+    io.cout <<= a_and_b | b_and_cin | a_and_cin
+```
+**Usage**: circuits are used by instancing them inside another definitions and
+  their ports are accessed using dot notation
+```python
+FA = FullAdder()
+```
+
+**Metaprogramming**: abstract over parameters by generating a circuit definition inside a closure
+```python
+def adder(n: int):
+    class Adder(Module):
+        io = IO(
+            a=Input(U.w(n)),
+            b=Input(U.w(n)),
+            cin=Input(Bool),
+            sum=Output(U.w(n)),
+            cout=Output(Bool),
+        )
+
+        FAs = [FullAdder().io for _ in range(n)]
+        carry = Wire(Vec(n + 1, Bool))
+        sum = Wire(Vec(n, Bool))
+
+        carry[0] <<= io.cin
+
+        for i in range(n):
+            FAs[i].a <<= io.a[i]
+            FAs[i].b <<= io.b[i]
+            FAs[i].cin <<= carry[i]
+            carry[i + 1] <<= FAs[i].cout
+            sum[i] <<= FAs[i].sum
+
+        io.sum <<= CatVecH2L(sum)
+        io.cout <<= carry[n]
+
+    return Adder()
+```
+
+# Operators
+## Infix operators
+All types support the following operators:
+- Equal `==`
+- Not Equal `!=`
+
+The `Bool` type supports the following logical operators.
+- And `&`
+- Or `|`
+- Exclusive or `^`
+- Not `~`
+
+The `Array` type family supports the following operator.
+- Dynamic bit selection `my_arry[add.O]` (select a bit dynamically using a magma value).
+
+The `Bits` type family supports the following logical operators.
+- And `&` (element-wise)
+- Or `|` (element-wise)
+- Exclusive or `^` (element-wise)
+- Not `~` (element-wise)
+- Logical right shift (with zeros) `>>`
+- Logical left shift (with zeros) `<<`
+
+The `UInt` and `SInt` types support all the logical operators
+as well as arithmetic and comparison operators.
+- Add `+`
+- Subtract/Negate `-`
+- Multiply `*`
+- Divide `/`
+- Less than `<`
+- Less than or equal `<=`
+- Greater than `>`
+- Greater than or equal `>=`
+
+Note that the the right shift operator when applied to an `SInt` becomes
+an arithmetic shift right operator (which replicates the sign bit as it shifts right).
+
+## Functional operators
+
+
+## Combinational
+```python
+# Mux(<选择信号>, <真输出>, <假输出>)
+io.z <<= Mux(io.sel, io.b, io.a)
+```
+
+## Sequential
+```python
+class Register(Module):
+    io = IO(
+        out=Output(U.w(32))
+    )
+
+    counter = RegInit(U.w(32)(0))
+    counter <<= counter + U(1)
+    io.out <<= counter
+```

docs/Datatypes/readme.md

@@ -0,0 +1,7 @@
+---
+sort: 3
+---
+
+# Data types
+
+{% include list.liquid %}

docs/Examples/examples.md

@@ -0,0 +1,5 @@
+# Examples
+
+## Simple ones
+
+## Advanced ones

docs/Examples/readme.md

@@ -0,0 +1,7 @@
+---
+sort: 8
+---
+
+# Examples
+
+{% include list.liquid %}

docs/Gemfile

@@ -0,0 +1,5 @@
+source "https://gems.ruby-china.com"
+gem "jekyll-rtd-theme"
+
+gem "github-pages", group: :jekyll_plugins
+gem "webrick", "~> 1.7"

docs/GettingStarted/GettingStarted.md

@@ -0,0 +1,18 @@
+# Gettting Started with PyHCL
+
+
+## Getting Started
+
+## Motivation
+
+## Python Guide
+
+
+
+
+
+
+
+
+
+

docs/GettingStarted/readme.md

@@ -0,0 +1,7 @@
+---
+sort: 2
+---
+
+# Getting Started
+
+{% include list.liquid %}

docs/Makefile

@@ -0,0 +1,16 @@
+DEBUG=JEKYLL_GITHUB_TOKEN=blank PAGES_API_URL=http://0.0.0.0
+
+default:
+	@gem install jekyll bundler && bundle install
+
+update:
+	@bundle update
+
+clean:
+	@bundle exec jekyll clean
+
+build: clean
+	@${DEBUG} bundle exec jekyll build --profile --config _config.yml,.debug.yml
+
+server: clean
+	@${DEBUG} bundle exec jekyll server --livereload --config _config.yml,.debug.yml

docs/OtherFeatures/OtherFeatures.md

@@ -0,0 +1,7 @@
+# Other Features
+
+## Pysv
+
+## DecoupleIO
+
+## ...

docs/OtherFeatures/readme.md

@@ -0,0 +1,7 @@
+---
+sort: 9
+---
+
+# Other Features
+
+{% include list.liquid %}

docs/Semantic/Semantic.md

@@ -0,0 +1,7 @@
+# Semantic
+
+## Assignments
+
+## Con
+
+## Rules

docs/Semantic/readme.md

@@ -0,0 +1,7 @@
+---
+sort: 5
+---
+
+# Semantic
+
+{% include list.liquid %}

docs/SequentialLogic/SequentialLogic.md

@@ -0,0 +1,5 @@
+# Sequential Logic
+
+## Registers
+
+## RAM/ROM

docs/SequentialLogic/readme.md

@@ -0,0 +1,7 @@
+---
+sort: 6
+---
+
+# Sequential Logic
+
+{% include list.liquid %}

docs/Structuring/Structuring.md

@@ -0,0 +1,9 @@
+# Structuring
+
+## module and hierarchy
+
+## Clock domains
+
+## Instamtiate Verilog IP
+
+## Parametrization

docs/Structuring/readme.md

@@ -0,0 +1,7 @@
+---
+sort: 4
+---
+
+# Structuring
+
+{% include list.liquid %}

docs/_config.yml

@@ -0,0 +1,14 @@
+title: PyHCL
+lang: en
+description: PyHCL is a hardware construct language. 
+
+remote_theme: rundocs/jekyll-rtd-theme
+
+readme_index:
+  with_frontmatter: true
+
+exclude:
+  - Makefile
+  - CNAME
+  - Gemfile
+  - Gemfile.lock  

docs/readme.md

@@ -0,0 +1,103 @@
+# Welcome to the PyHCL Documentation
+
+## site purpose and structure
+
+This site presents the PyHCL language and how to use it on concrete examples.
+
+## What is PyHCL
+
+PyHCL is a hardware construct language like [Chisel](https://github.com/freechipsproject/chisel3) but more lightweight and more relaxed to use.
+As a novel hardware construction framework embedded in Python, PyHCL supports several useful features include object-oriented, functional programming,
+and dynamically typed objects.
+
+The goal of PyHCL is providing a complete design and verification tool flow for heterogeneous computing systems flexibly using the same design methodology.
+
+PyHCL is powered by [FIRRTL](https://github.com/freechipsproject/firrtl), an intermediate representation for digital circuit design. With the FIRRTL 
+compiler framework, PyHCL-generated circuits can be compiled to the widely-used HDL Verilog.  
+
+## Advantage of using SpinalHDL over Verilog/VHDL
+
+## Similar Projects
+
+* [autofpga](https://github.com/ZipCPU/autofpga) - C++, A utility for Composing FPGA designs from Peripherals
+* [BinPy](https://github.com/BinPy/BinPy) - Python, An electronic simulation library
+* [blarney](https://github.com/blarney-lang/blarney) - Haskell, HCL
+* [bsc](https://github.com/B-Lang-org/bsc) - Haskell, C++, BSV - Bluespec Compiler
+* [chisel](https://chisel.eecs.berkeley.edu/) - 2012-?, Scala, HCL
+* [Chips-2.0](https://github.com/dawsonjon/Chips-2.0) - , , FPGA Design Suite based on C to Verilog design flow
+* [circt](https://github.com/llvm/circt) - 2020-?, C++/LLVM, compiler infrastructure
+* [circuitgraph](https://github.com/circuitgraph/circuitgraph) - Tools for working with circuits as graphs in python
+* [concat](https://github.com/conal/concat) - 2016-?, Haskell, Haskell to hardware
+* [DUH](https://github.com/sifive/duh) - JS, simple convertor between verilog/scala/ipxact
+* [DFiant](https://github.com/DFiantHDL/DFiant) 2019-?, Scala, dataflow based HDL
+* [edalize](https://github.com/olofk/edalize) - 2018-?, Python, abstraction layer for eda tools
+* [garnet](https://github.com/StanfordAHA/garnet) -2018-?, Python, Coarse-Grained Reconfigurable Architecture generator based on magma
+* [hammer](https://github.com/ucb-bar/hammer) - 2017-?, Python, Highly Agile Masks Made Effortlessly from RTL
+* [heterocl](https://github.com/cornell-zhang/heterocl) - 2017-?, C++, A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing
+* [hoodlum](https://github.com/tcr/hoodlum) - 2016-?, Rust, HCL
+* [ILAng](https://github.com/Bo-Yuan-Huang/ILAng) - modeling and verification platform for SoCs where Instruction-Level Abstraction (ILA) is used as the formal model for hardware components.
+* :skull: [jhdl](https://github.com/larsjoost/jhdl) - ?-2017, C++ Verilog/VHDL -> systemC, prototype
+* [Kactus2](http://funbase.cs.tut.fi) - IP-core packager
+* [kratos](https://github.com/Kuree/kratos) - C++/Python, hardware generator/simulator
+* [lgraph](https://github.com/masc-ucsc/lgraph) - C, generic graph library
+* [llhd](https://github.com/fabianschuiki/llhd) - Rust, HCL
+* [livehd](https://github.com/masc-ucsc/livehd) - mainly C++, An infrastructure designed for Live Hardware Development.
+* [Lucid HDL in Alchitry-Labs](https://github.com/alchitry/Alchitry-Labs) - Custom language and IDE inspired by Verilog
+* [magma](https://github.com/phanrahan/magma/) - 2017-?, Python, HCL
+* [migen](https://github.com/m-labs/migen) - 2013-?, Python, HCL
+* [mockturtle](https://github.com/lsils/mockturtle) - logic network library
+* [moore](https://github.com/fabianschuiki/moore) - Rust, HDL -> model compiler
+* [MyHDL](https://github.com/myhdl/myhdl) - 2004-?, Python, Process based HDL
+* [nmigen](https://github.com/m-labs/nmigen) -, Python, A refreshed Python toolbox for building complex digital hardware
+* [OpenTimer](https://github.com/OpenTimer/OpenTimer) - , C++,  A High-Performance Timing Analysis Tool for VLSI Systems
+* [percy](https://github.com/whaaswijk/percy) - Collection of different synthesizers and exact synthesis methods for use in applications such as circuit resynthesis and design exploration.
+* [PyChip-py-hcl](https://github.com/scutdig/PyChip-py-hcl) - , Python, Chisel3 like HCL
+* [pygears](https://github.com/bogdanvuk/pygears) - , Python, function style HDL generator
+* [PyMTL3](https://github.com/cornell-brg/pymtl3) 2018-?
+* [PyMTL](https://github.com/cornell-brg/pymtl) - 2014-?, Python, Process based HDL
+* [PipelineC](https://github.com/JulianKemmerer/PipelineC) - 2018-?, Python, C++ HLS-like automatic pipelining as a language construct/compiler
+* [PyRTL](https://github.com/UCSBarchlab/PyRTL) - 2015-?, Python, HCL
+* [Pyverilog](https://github.com/PyHDI/Pyverilog) - 2013-? Python-based Hardware Design Processing Toolkit for Verilog HDL
+* [rogue](https://github.com/slaclab/rogue) , C++/Python - Hardware Abstraction & Data Acquisition System
+* [sail](https://github.com/rems-project/sail) 2018-?, (OCaml, Standard ML, Isabelle) - architecture definition language
+* [spatial](https://github.com/stanford-ppl/spatial) - Scala, an Argon DSL like, high level abstraction
+* [SpinalHDL](https://github.com/SpinalHDL/SpinalHDL) - 2015-?, Scala, HCL
+* [Silice](https://github.com/sylefeb/Silice) - ?, C++, Custom HDL
+* :skull: [SyDpy](https://github.com/bogdanvuk/sydpy) - ?-2016, Python, HCL and verif. framework operating on TML/RTL level
+* [systemrdl-compiler](https://github.com/SystemRDL/systemrdl-compiler) - Python,c++, register description language compiler
+* [UHDM](https://github.com/alainmarcel/UHDM) - C++ SystemVerilog -> C++ model
+* :skull: [Verilog.jl](https://github.com/interplanetary-robot/Verilog.jl) - 2017-2017, Julia, simple Julia to Verilog transpiler
+* [veriloggen](https://github.com/PyHDI/veriloggen) - 2015-?, Python, Verilog centric HCL with HLS like features
+* :skull:  [wyre](https://github.com/nickmqb/wyre) - 2020-2020, Mupad, Minimalistic HDL
+* [phi](https://github.com/donn/Phi) - 2019-?, custom language, llvm based compiler of custom hdl
+* [prga](https://github.com/PrincetonUniversity/prga) - 2019-?. Python, prototyping platform with integrated yosys
+
+
+
+
+
+See the sidebar for various pages.
+<!-- 关于模板说明，docs为整个文档的根目录，其下文件夹为一级目录, 每一级目录的readme.md为该级目录的索引 -->
+
+<!--  pkill -f jekyll 杀
+      bundle exec jekyll serve 开
+-->
+
+* [About PyHCL](./AboutPyHCL/readme.md)
+* [Data types](./Datatypes/readme.md)
+* [Examples](./Examples/readme.md)
+* [Getting Stated](./GettingStarted/readme.md)
+
+<!-- 
+仿照spinalhdl来写
+.关于：说明
+.开始：安装
+.数据类型：Bool，bits，这些
+.语法：赋值，选择，
+.等级：module，，，
+.时序逻辑：多时钟域
+.仿真
+.例子：滤波器设计。。。
+.提升：
+ -->
+