forked from opendacs/PyHCL
test_firrtl_ir: add def tests (instance memory node register wire) (#21)
* test_firrtl_ir: add def tests (instance memory node register wire) * test_firrtl_ir: make style check happy
This commit is contained in:
parent
bf6d12045a
commit
4809e03592
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@ -32,7 +32,7 @@ class DefMemReadPort(Statement):
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self.clock_ref.serialize(output)
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class DefMemWriteRead(Statement):
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class DefMemWritePort(Statement):
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def __init__(self, name, mem_ref, index_ref, clock_ref):
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self.name = name
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self.mem_ref = mem_ref
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@ -33,8 +33,8 @@ class DefInitRegister(Statement):
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output.write(b", ")
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self.clock_ref.serialize(output)
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output.write(b" with :\n")
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output.write(serialize_str(" " * indent))
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output.write(b" (")
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output.write(serialize_str(" " * (indent + 1)))
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output.write(b"reset => (")
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self.reset_ref.serialize(output)
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output.write(b", ")
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self.init_ref.serialize(output)
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@ -1,3 +1,4 @@
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from .stmt.definition import DefinitionTypeChecker
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from .stmt.block import BlockTypeChecker
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from .stmt.conditionally import ConditionallyTypeChecker
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from ..stmt import Statement
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@ -27,6 +28,7 @@ final_map = {
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**ConnectTypeChecker.connect_checker_map,
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**ConditionallyTypeChecker.conditionally_checker_map,
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**BlockTypeChecker.block_checker_map,
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**DefinitionTypeChecker.definition_checker_map,
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# simple statement
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EmptyStmt: true,
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@ -31,8 +31,8 @@ def checker(accessor):
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@checker(SubField)
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def _(sub_field):
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from .. import check
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if not check(sub_field.bundle_ref):
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from .. import check_all_expr
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if not check_all_expr(sub_field.bundle_ref):
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return False
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if not type_in(sub_field.bundle_ref.tpe, BundleType):
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@ -54,8 +54,8 @@ def _(sub_field):
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@checker(SubIndex)
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def _(sub_index):
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from .. import check
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if not check(sub_index.vector_ref):
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from .. import check_all_expr
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if not check_all_expr(sub_index.vector_ref):
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return False
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if not type_in(sub_index.vector_ref.tpe, VectorType):
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@ -169,8 +169,8 @@ def _(binary_bit):
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@checker(Not)
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def _(n):
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from .. import check
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if not check(n.arg):
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from .. import check_all_expr
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if not check_all_expr(n.arg):
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return False
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if not check_all_same_uint_sint(n.arg.tpe):
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@ -188,8 +188,8 @@ def _(n):
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@checker(Neg)
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def _(neg):
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from .. import check
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if not check(neg.arg):
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from .. import check_all_expr
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if not check_all_expr(neg.arg):
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return False
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if not check_all_same_uint_sint(neg.arg.tpe):
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@ -228,8 +228,8 @@ def _(cat):
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@checker(Bits)
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def _(bits):
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from .. import check
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if not check(bits.ir_arg):
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from .. import check_all_expr
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if not check_all_expr(bits.ir_arg):
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return False
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if not check_all_same_uint_sint(bits.ir_arg.tpe):
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@ -253,8 +253,8 @@ def _(bits):
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@checker(AsUInt)
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def _(as_uint):
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from .. import check
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if not check(as_uint.arg):
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from .. import check_all_expr
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if not check_all_expr(as_uint.arg):
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return False
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if not type_in(as_uint.arg.tpe, UIntType, SIntType, ClockType):
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@ -274,8 +274,8 @@ def _(as_uint):
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@checker(AsSInt)
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def _(as_sint):
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from .. import check
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if not check(as_sint.arg):
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from .. import check_all_expr
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if not check_all_expr(as_sint.arg):
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return False
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if not type_in(as_sint.arg.tpe, UIntType, SIntType, ClockType):
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@ -295,8 +295,8 @@ def _(as_sint):
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@checker(Shl)
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def _(shl):
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from .. import check
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if not check(shl.ir_arg):
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from .. import check_all_expr
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if not check_all_expr(shl.ir_arg):
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return False
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if not check_all_same_uint_sint(shl.ir_arg.tpe, shl.tpe):
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@ -311,8 +311,8 @@ def _(shl):
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@checker(Shr)
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def _(shr):
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from .. import check
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if not check(shr.ir_arg):
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from .. import check_all_expr
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if not check_all_expr(shr.ir_arg):
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return False
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if not check_all_same_uint_sint(shr.ir_arg.tpe, shr.tpe):
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@ -0,0 +1,171 @@
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from ...shortcuts import uw
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from ...type_measurer import equal
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from ...stmt.defn.circuit import DefCircuit
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from ...stmt.defn.instance import DefInstance
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from ...stmt.defn.memory import DefMemory, DefMemReadPort, DefMemWritePort
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from ...stmt.defn.module import DefModule, InputPort, OutputPort, DefExtModule
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from ...stmt.defn.node import DefNode
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from ...type import VectorType, ClockType, UIntType
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from ..utils import type_in
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from ...stmt.defn.register import DefRegister, DefInitRegister
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from ...stmt.defn.wire import DefWire
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class DefinitionTypeChecker(object):
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definition_checker_map = {}
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@staticmethod
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def check(op_obj):
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try:
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return DefinitionTypeChecker \
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.definition_checker_map[type(op_obj)](op_obj)
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except KeyError:
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raise NotImplementedError(type(op_obj))
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def checker(definition):
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def f(func):
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DefinitionTypeChecker.definition_checker_map[definition] = func
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return func
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return f
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###############################################################
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# TYPE CHECKERS #
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###############################################################
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@checker(DefWire)
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def _(_):
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return True
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@checker(DefInstance)
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def _(_):
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return True
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@checker(DefRegister)
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def _(reg):
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from ...type_checker import check_all_expr
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if not check_all_expr(reg.clock_ref):
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return False
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if not type_in(reg.clock_ref.tpe, ClockType):
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return False
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return True
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@checker(DefInitRegister)
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def _(reg):
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from ...type_checker import check_all_expr
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if not check_all_expr(reg.clock_ref, reg.reset_ref, reg.init_ref):
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return False
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if not type_in(reg.clock_ref.tpe, ClockType):
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return False
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if not equal(reg.reset_ref.tpe, uw(1)):
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return False
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if not equal(reg.init_ref.tpe, reg.tpe):
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return False
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return True
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@checker(DefNode)
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def _(node):
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from ...type_checker import check_all_expr
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if not check_all_expr(node.expr_ref):
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return False
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return True
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@checker(DefMemory)
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def _(mem):
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if not type_in(mem.tpe, VectorType):
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return False
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return True
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@checker(DefMemReadPort)
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def _(mem_read):
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from ...type_checker import check_all_expr
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if not check_all_expr(mem_read.mem_ref, mem_read.index_ref,
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mem_read.clock_ref):
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return False
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if not type_in(mem_read.mem_ref.tpe, VectorType):
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return False
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if not type_in(mem_read.clock_ref.tpe, ClockType):
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return False
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if not type_in(mem_read.index_ref.tpe, UIntType):
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return False
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return True
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@checker(DefMemWritePort)
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def _(mem_write):
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from ...type_checker import check_all_expr
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if not check_all_expr(mem_write.mem_ref, mem_write.index_ref,
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mem_write.clock_ref):
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return False
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if not type_in(mem_write.mem_ref.tpe, VectorType):
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return False
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if not type_in(mem_write.clock_ref.tpe, ClockType):
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return False
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if not type_in(mem_write.index_ref.tpe, UIntType):
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return False
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return True
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@checker(DefModule)
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def _(mod):
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from ...type_checker import check_all_stmt
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if not check_all_stmt(mod.body):
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return False
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for port in mod.ports:
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if not type_in(port, InputPort, OutputPort):
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return False
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return True
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@checker(DefExtModule)
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def _(mod):
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for port in mod.ports:
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if not type_in(port, InputPort, OutputPort):
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return False
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return True
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@checker(DefCircuit)
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def _(circuit):
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from ...type_checker import check_all_stmt
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if not check_all_stmt(*circuit.def_modules):
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return False
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name_found = False
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for mod in circuit.def_modules:
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if not type_in(mod, DefModule, DefExtModule):
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return False
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if mod.name == circuit.name:
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name_found = True
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if not name_found:
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return False
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return True
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@ -13,7 +13,10 @@ def test_conditionally_basis():
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cn = Conditionally(n("a", uw(1)), s1, s2)
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assert ConditionallyTypeChecker.check(cn)
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assert check(cn)
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serialize_stmt_equal(cn, "when a :\n skip\nelse :\n a <= b")
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serialize_stmt_equal(cn, "when a :\n"
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" skip\n"
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"else :\n"
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" a <= b")
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s1 = Block([
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Connect(n("a", uw(8)), n("b", uw(8))),
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assert ConditionallyTypeChecker.check(cn)
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assert check(cn)
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serialize_stmt_equal(
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cn, 'when UInt<1>("1") :\n a <= b\n c <= d\nelse :\n skip')
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cn, 'when UInt<1>("1") :\n'
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' a <= b\n'
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' c <= d\n'
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'else :\n'
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' skip')
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def test_conditionally_type_wrong():
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@ -0,0 +1,10 @@
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from py_hcl.firrtl_ir.stmt.defn.instance import DefInstance
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from py_hcl.firrtl_ir.type_checker import check, DefinitionTypeChecker
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from ...utils import serialize_stmt_equal
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def test_instance_basis():
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i1 = DefInstance("i1", "ALU")
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assert DefinitionTypeChecker.check(i1)
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assert check(i1)
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serialize_stmt_equal(i1, 'inst i1 of ALU')
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@ -0,0 +1,131 @@
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from py_hcl.firrtl_ir.shortcuts import vec, uw, bdl, n, u, w, s
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from py_hcl.firrtl_ir.stmt.defn.memory import DefMemory, \
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DefMemWritePort, DefMemReadPort
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from py_hcl.firrtl_ir.type import ClockType
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from py_hcl.firrtl_ir.type_checker import check, DefinitionTypeChecker
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from ...utils import serialize_stmt_equal
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def test_memory_basis():
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mem = DefMemory("m", vec(uw(8), 10))
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assert DefinitionTypeChecker.check(mem)
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assert check(mem)
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serialize_stmt_equal(mem, 'cmem m : UInt<8>[10]')
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mem = DefMemory("m", vec(bdl(a=(uw(8), False)), 10))
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assert DefinitionTypeChecker.check(mem)
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assert check(mem)
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serialize_stmt_equal(mem, 'cmem m : {a : UInt<8>}[10]')
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def test_memory_type_wrong():
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mem = DefMemory("m", bdl(a=(vec(uw(8), 10), False)))
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assert not DefinitionTypeChecker.check(mem)
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assert not check(mem)
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mem = DefMemory("m", uw(9))
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assert not DefinitionTypeChecker.check(mem)
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assert not check(mem)
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def test_read_port_basis():
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mem_ref = n("m", vec(uw(8), 10))
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mr = DefMemReadPort("mr", mem_ref, u(2, w(8)), n("clock", ClockType()))
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assert DefinitionTypeChecker.check(mr)
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assert check(mr)
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serialize_stmt_equal(mr, 'read mport mr = m[UInt<8>("2")], clock')
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mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
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mr = DefMemReadPort("mr", mem_ref, n("a", uw(2)), n("clock", ClockType()))
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assert DefinitionTypeChecker.check(mr)
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assert check(mr)
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serialize_stmt_equal(mr, 'read mport mr = m[a], clock')
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def test_read_port_clock_wrong():
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mem_ref = n("m", vec(uw(8), 10))
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mr = DefMemReadPort("mr", mem_ref, u(2, w(8)), n("clock", uw(1)))
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assert not DefinitionTypeChecker.check(mr)
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assert not check(mr)
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mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
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mr = DefMemReadPort("mr", mem_ref, n("a", uw(2)), u(0, w(1)))
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assert not DefinitionTypeChecker.check(mr)
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assert not check(mr)
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def test_read_port_index_wrong():
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mem_ref = n("m", vec(uw(8), 10))
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mr = DefMemReadPort("mr", mem_ref, s(2, w(8)), n("clock", ClockType()))
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assert not DefinitionTypeChecker.check(mr)
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assert not check(mr)
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mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
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mr = DefMemReadPort("mr", mem_ref,
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n("a", vec(uw(1), 10)), n("clock", ClockType()))
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assert not DefinitionTypeChecker.check(mr)
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assert not check(mr)
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def test_read_port_mem_wrong():
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mem_ref = n("m", bdl(a=(vec(uw(8), 10), False)))
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mr = DefMemReadPort("mr", mem_ref, u(2, w(8)), n("clock", ClockType()))
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assert not DefinitionTypeChecker.check(mr)
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assert not check(mr)
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mem_ref = n("m", uw(9))
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mr = DefMemReadPort("mr", mem_ref, n("a", uw(2)), n("clock", ClockType()))
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assert not DefinitionTypeChecker.check(mr)
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assert not check(mr)
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def test_write_port_basis():
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mem_ref = n("m", vec(uw(8), 10))
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mw = DefMemWritePort("mw", mem_ref, u(2, w(8)), n("clock", ClockType()))
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assert DefinitionTypeChecker.check(mw)
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assert check(mw)
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serialize_stmt_equal(mw, 'write mport mw = m[UInt<8>("2")], clock')
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mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
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mw = DefMemWritePort("mw", mem_ref, n("a", uw(2)), n("clock", ClockType()))
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assert DefinitionTypeChecker.check(mw)
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assert check(mw)
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serialize_stmt_equal(mw, 'write mport mw = m[a], clock')
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def test_write_port_clock_wrong():
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mem_ref = n("m", vec(uw(8), 10))
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mw = DefMemWritePort("mw", mem_ref, u(2, w(8)), n("clock", uw(1)))
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assert not DefinitionTypeChecker.check(mw)
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assert not check(mw)
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mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
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mw = DefMemWritePort("mw", mem_ref, n("a", uw(2)), u(0, w(1)))
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assert not DefinitionTypeChecker.check(mw)
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assert not check(mw)
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def test_write_port_index_wrong():
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mem_ref = n("m", vec(uw(8), 10))
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mw = DefMemWritePort("mw", mem_ref, s(2, w(8)), n("clock", ClockType()))
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assert not DefinitionTypeChecker.check(mw)
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assert not check(mw)
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mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
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mw = DefMemWritePort("mw", mem_ref,
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n("a", vec(uw(1), 10)), n("clock", ClockType()))
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assert not DefinitionTypeChecker.check(mw)
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assert not check(mw)
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def test_write_port_mem_wrong():
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mem_ref = n("m", bdl(a=(vec(uw(8), 10), False)))
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mw = DefMemWritePort("mw", mem_ref, u(2, w(8)), n("clock", ClockType()))
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assert not DefinitionTypeChecker.check(mw)
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assert not check(mw)
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mem_ref = n("m", uw(9))
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mw = DefMemWritePort("mw", mem_ref,
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n("a", uw(2)), n("clock", ClockType()))
|
||||
assert not DefinitionTypeChecker.check(mw)
|
||||
assert not check(mw)
|
|
@ -0,0 +1,27 @@
|
|||
from py_hcl.firrtl_ir.expr.accessor import SubIndex
|
||||
from py_hcl.firrtl_ir.shortcuts import n, s, w, vec, uw
|
||||
from py_hcl.firrtl_ir.stmt.defn.node import DefNode
|
||||
from py_hcl.firrtl_ir.type_checker import check, DefinitionTypeChecker
|
||||
from ...utils import serialize_stmt_equal
|
||||
|
||||
|
||||
def test_node_basis():
|
||||
node = DefNode("n1", s(20, w(6)))
|
||||
assert DefinitionTypeChecker.check(node)
|
||||
assert check(node)
|
||||
serialize_stmt_equal(node, 'node n1 = SInt<6>("14")')
|
||||
|
||||
node = DefNode("n2", SubIndex(n("v", vec(uw(8), 10)), 7, uw(8)))
|
||||
assert DefinitionTypeChecker.check(node)
|
||||
assert check(node)
|
||||
serialize_stmt_equal(node, 'node n2 = v[7]')
|
||||
|
||||
|
||||
def test_node_expr_wrong():
|
||||
node = DefNode("n1", s(20, w(5)))
|
||||
assert not DefinitionTypeChecker.check(node)
|
||||
assert not check(node)
|
||||
|
||||
node = DefNode("n2", SubIndex(n("v", vec(uw(8), 10)), 10, uw(8)))
|
||||
assert not DefinitionTypeChecker.check(node)
|
||||
assert not check(node)
|
|
@ -0,0 +1,79 @@
|
|||
from py_hcl.firrtl_ir.shortcuts import n, s, w, vec, uw, sw, u
|
||||
from py_hcl.firrtl_ir.stmt.defn.register import DefRegister, DefInitRegister
|
||||
from py_hcl.firrtl_ir.type import ClockType
|
||||
from py_hcl.firrtl_ir.type_checker import check, DefinitionTypeChecker
|
||||
from ...utils import serialize_stmt_equal
|
||||
|
||||
|
||||
def test_register_basis():
|
||||
r1 = DefRegister("r1", uw(8), n("clock", ClockType()))
|
||||
assert DefinitionTypeChecker.check(r1)
|
||||
assert check(r1)
|
||||
serialize_stmt_equal(r1, 'reg r1 : UInt<8>, clock')
|
||||
|
||||
r2 = DefRegister("r2", vec(uw(8), 10), n("clock", ClockType()))
|
||||
assert DefinitionTypeChecker.check(r2)
|
||||
assert check(r2)
|
||||
serialize_stmt_equal(r2, 'reg r2 : UInt<8>[10], clock')
|
||||
|
||||
|
||||
def test_register_clock_wrong():
|
||||
r1 = DefRegister("r1", uw(8), n("clock", uw(1)))
|
||||
assert not DefinitionTypeChecker.check(r1)
|
||||
assert not check(r1)
|
||||
|
||||
r2 = DefRegister("r2", vec(uw(8), 10), n("clock", sw(1)))
|
||||
assert not DefinitionTypeChecker.check(r2)
|
||||
assert not check(r2)
|
||||
|
||||
|
||||
def test_init_register_basis():
|
||||
r1 = DefInitRegister("r1", uw(8),
|
||||
n("clock", ClockType()), n("r", uw(1)), u(5, w(8)))
|
||||
assert DefinitionTypeChecker.check(r1)
|
||||
assert check(r1)
|
||||
serialize_stmt_equal(r1, 'reg r1 : UInt<8>, clock with :\n'
|
||||
' reset => (r, UInt<8>("5"))')
|
||||
|
||||
r2 = DefInitRegister("r2", sw(8),
|
||||
n("clock", ClockType()), u(0, w(1)), s(5, w(8)))
|
||||
assert DefinitionTypeChecker.check(r2)
|
||||
assert check(r2)
|
||||
serialize_stmt_equal(r2, 'reg r2 : SInt<8>, clock with :\n'
|
||||
' reset => (UInt<1>("0"), SInt<8>("5"))')
|
||||
|
||||
|
||||
def test_init_register_clock_wrong():
|
||||
r1 = DefInitRegister("r1", uw(8),
|
||||
n("clock", uw(1)), n("r", uw(1)), u(5, w(8)))
|
||||
assert not DefinitionTypeChecker.check(r1)
|
||||
assert not check(r1)
|
||||
|
||||
r2 = DefInitRegister("r2", sw(8),
|
||||
n("clock", sw(1)), u(0, w(1)), s(5, w(8)))
|
||||
assert not DefinitionTypeChecker.check(r2)
|
||||
assert not check(r2)
|
||||
|
||||
|
||||
def test_init_register_reset_wrong():
|
||||
r1 = DefInitRegister("r1", uw(8),
|
||||
n("clock", ClockType()), n("r", sw(1)), u(5, w(8)))
|
||||
assert not DefinitionTypeChecker.check(r1)
|
||||
assert not check(r1)
|
||||
|
||||
r2 = DefInitRegister("r2", sw(8),
|
||||
n("clock", ClockType()), s(0, w(1)), s(5, w(8)))
|
||||
assert not DefinitionTypeChecker.check(r2)
|
||||
assert not check(r2)
|
||||
|
||||
|
||||
def test_init_register_type_not_match():
|
||||
r1 = DefInitRegister("r1", uw(8),
|
||||
n("clock", ClockType()), n("r", uw(1)), s(5, w(8)))
|
||||
assert not DefinitionTypeChecker.check(r1)
|
||||
assert not check(r1)
|
||||
|
||||
r2 = DefInitRegister("r2", uw(8),
|
||||
n("clock", ClockType()), u(0, w(1)), s(5, w(8)))
|
||||
assert not DefinitionTypeChecker.check(r2)
|
||||
assert not check(r2)
|
|
@ -0,0 +1,16 @@
|
|||
from py_hcl.firrtl_ir.shortcuts import uw, bdl, sw
|
||||
from py_hcl.firrtl_ir.stmt.defn.wire import DefWire
|
||||
from py_hcl.firrtl_ir.type_checker import check, DefinitionTypeChecker
|
||||
from ...utils import serialize_stmt_equal
|
||||
|
||||
|
||||
def test_wire_basis():
|
||||
wire = DefWire("w1", uw(8))
|
||||
assert DefinitionTypeChecker.check(wire)
|
||||
assert check(wire)
|
||||
serialize_stmt_equal(wire, 'wire w1 : UInt<8>')
|
||||
|
||||
wire = DefWire("w2", bdl(a=(uw(8), True), b=(sw(8), False)))
|
||||
assert DefinitionTypeChecker.check(wire)
|
||||
assert check(wire)
|
||||
serialize_stmt_equal(wire, 'wire w2 : {flip a : UInt<8>, b : SInt<8>}')
|
|
@ -1,6 +1,8 @@
|
|||
from py_hcl.firrtl_ir.stmt.empty import EmptyStmt
|
||||
from py_hcl.firrtl_ir.type_checker import check
|
||||
from ..utils import serialize_stmt_equal
|
||||
|
||||
|
||||
def test_empty_serialize():
|
||||
serialize_stmt_equal(EmptyStmt(), "skip")
|
||||
assert check(EmptyStmt())
|
||||
|
|
Loading…
Reference in New Issue