firrtl_ir: add field

py_hcl/firrtl_ir/field.py

@@ -0,0 +1,27 @@
+"""
+The field module provides information about the field
+in BundleType.
+
+Fields are allowed to be flipped, indicating that it's
+opposite direction to the BundleType.
+
+Each field includes
+  name:        individual name of the field;
+  type:        defined type;
+  orientation: flipped or not.
+"""
+from .utils import serialize_str
+
+
+class Field(object):
+    def __init__(self, name, tpe, is_flipped=False):
+        self.name = name
+        self.tpe = tpe
+        self.is_flipped = is_flipped
+
+    def serialize(self, output):
+        if self.is_flipped:
+            output.write(b"flip ")
+        output.write(serialize_str(self.name))
+        output.write(b" : ")
+        self.tpe.serialize(output)

py_hcl/firrtl_ir/tpe.py

@@ -1,12 +1,14 @@
 """
-The tpe module provides type nodes in firrtl IR.
+The tpe module provides type nodes in FIRRTL IR.
 
 At the top level of types include UnknownType, GroundType, AggregateType.
 GroundType acts as a primitive type, and AggregateType is similar to a
 data structure composed of GroundType.
 
-GroundType includes UIntType, unsigned integer; SIntType, signed integer;
-and ClockType, represents the clock.
+GroundType includes
+  UIntType:  unsigned integer;
+  SIntType:  signed integer;
+  ClockType: represents the clock.
 
 AggregateType includes BundleType, similar to the structs in high-level
 languages, composed of various fields of different types. VectorType
@@ -58,9 +60,10 @@ class BundleType(AggregateType):
 
     def serialize(self, output):
         output.write(b"{")
-        for f in self.fields:
+        for f in self.fields[:-1]:
             f.serialize(output)
             output.write(b", ")
+        self.fields[-1].serialize(output)
         output.write(b"}")
 
 

py_hcl/firrtl_ir/utils.py

@@ -1,2 +1,6 @@
 def serialize_num(num):
-    return bytes(str(num), 'utf-8')
+    return serialize_str(str(num))
+
+
+def serialize_str(s):
+    return bytes(s, 'utf-8')

py_hcl/firrtl_ir/width.py

@@ -1,7 +1,6 @@
 """
-The tpe module provides bit width information for UIntType
+The width module provides bit width information for UIntType
 and SIntType.
-
 """
 
 from .utils import serialize_num

tests/test_firrtl_ir/test_type.py

@@ -1,4 +1,4 @@
-from py_hcl.firrtl_ir import tpe, width
+from py_hcl.firrtl_ir import tpe, width, field
 from .utils import serialize_equal
 
 
@@ -37,3 +37,33 @@ def test_vector_type():
 
     vt = tpe.VectorType(tpe.VectorType(tpe.VectorType(vt, 42), 7), 9)
     serialize_equal(vt, "UInt<8>[16][32][42][7][9]")
+
+
+def test_bundle_type():
+    bd = tpe.BundleType([
+        field.Field("a", tpe.UIntType(width.IntWidth(8))),
+        field.Field("b", tpe.UIntType(width.IntWidth(8))),
+        field.Field("c", tpe.UIntType(width.IntWidth(8)), True),
+    ])
+    serialize_equal(bd, "{a : UInt<8>, b : UInt<8>, flip c : UInt<8>}")
+
+    vt = tpe.VectorType(tpe.UIntType(width.IntWidth(8)), 16)
+    bd = tpe.BundleType([
+        field.Field("a", vt),
+        field.Field("b", tpe.UIntType(width.IntWidth(8)), True),
+        field.Field("c", tpe.VectorType(vt, 32)),
+    ])
+    serialize_equal(
+        bd, "{a : UInt<8>[16], flip b : UInt<8>, c : UInt<8>[16][32]}"
+    )
+
+    # TODO: Is it valid?
+    bd = tpe.BundleType([
+        field.Field("l1", tpe.BundleType([
+            field.Field("l2", tpe.BundleType([
+                field.Field("l3", tpe.UIntType(width.IntWidth(8)), True)
+            ])),
+            field.Field("vt", vt),
+        ]))
+    ])
+    serialize_equal(bd, "{l1 : {l2 : {flip l3 : UInt<8>}, vt : UInt<8>[16]}}")