forked from opendacs/PyHCL
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lx071
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0fd231483e
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from pyhcl import *
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from pysv import sv, DataType, Reference
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from pyhcl.simulator import Simlite, DpiConfig
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from queue import Queue
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import random
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class Add(BlackBox):
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io = IO(
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in1=Input(U.w(32)),
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in2=Input(U.w(32)),
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out=Output(U.w(32))
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)
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@sv(a=DataType.UInt, b=DataType.UInt, return_type=Reference(x=DataType.UInt))
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def fn(a, b):
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return a + b
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addpysvmodule(Add, fn) # 黑盒与函数 # 转换得到.sv/bbox/Add.sv，（SV里调用python函数）
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compile_and_binding_all() # 编译得到共享库 到.build文件夹下, 生成 SV binding文件 （.sv/pkg/pysv_pkg.sv）
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class Top(Module):
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io = IO(
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a=Input(U.w(32)),
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b=Input(U.w(32)),
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c=Output(U.w(32))
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)
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add = Add()
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add.io.in1 <<= io.a
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add.io.in2 <<= io.b
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io.c <<= add.io.out
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# 每次给输入端口赋值, 跑一个时间单位
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def test_step(s):
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s.start()
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s.step([20, 20])
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print("time: %d\t\tresult:%s" % (s.cnt, s.getRes()))
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s.step([15, 10])
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print("time: %d\t\tresult:%s" % (s.cnt, s.getRes()))
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s.step([1000, 1])
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print("time: %d\t\tresult:%s" % (s.cnt, s.getRes()))
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s.step([999, 201])
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s.stop()
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def test_task(s):
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tasks = []
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tasks.append([20, 20])
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tasks.append([15, 10])
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tasks.append([1000, 1])
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tasks.append([999, 201])
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s.start_task('Top', tasks)
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def randomInput(ifn):
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fd = open(ifn, "w")
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instr = ""
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for i in range(100):
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instr += "0 " + str(random.randint(1, 2000)) + ' ' + str(random.randint(1, 2000)) + "\n"
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instr = instr + "-1\n"
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fd.write(instr)
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fd.close()
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def test_file(s):
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ifn = f"../myTests/tmp/Top_inputs"
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ofn = f"../myTests/tmp/Top_outputs"
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randomInput(ifn)
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s.start(mode="task", ofn=ofn, ifn=ifn)
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pass
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def main():
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cfg = DpiConfig()
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# Emitter.dumpVerilog(Emitter.dump(Emitter.emit(Top()), "Top.fir"))
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s = Simlite(Top(), dpiconfig=cfg, debug=True)
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# test_step(s)
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# test_task(s)
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test_file(s)
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s.close()
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if __name__ == '__main__':
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cfg = DpiConfig()
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# Emitter.dumpVerilog(Emitter.dump(Emitter.emit(Top()), "Top.fir"))
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s = Simlite(Top(), dpiconfig=cfg, debug=True)
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s.start()
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s.step([20, 20])
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s.step([15, 10])
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s.step([1000, 1])
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s.step([999, 201])
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s.close()
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@ -1,66 +0,0 @@
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from pyhcl import *
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from pysv import sv, DataType, Reference
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from pyhcl.simulator import DpiConfig
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from queue import Queue
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from pyhcl.simulator.simlite_verilog import Simlite
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import random
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# 每次给输入端口赋值, 跑一个时间单位
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def test_step(s):
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s.start()
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s.step([0, 0, 20, 20])
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print("kkk")
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print("time: %d\t\tresult:%s" % (s.cnt, s.getRes()))
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s.step([1, 0, 15, 10])
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print("time: %d\t\tresult:%s" % (s.cnt, s.getRes()))
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s.step([0, 0, 1000, 1])
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print("time: %d\t\tresult:%s" % (s.cnt, s.getRes()))
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s.step([1, 0, 999, 201])
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s.stop()
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def test_task(s):
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tasks = []
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tasks.append([0, 0, 20, 20])
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tasks.append([1, 0, 15, 10])
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tasks.append([0, 0, 1000, 1])
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tasks.append([1, 0, 999, 201])
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s.start_task('Top', tasks)
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def randomInput(ifn):
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fd = open(ifn, "w")
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instr = ""
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for i in range(100):
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instr += "0 0 0 " + str(random.randint(1, 2000)) + ' ' + str(random.randint(1, 2000)) + "\n"
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instr = instr + "-1\n"
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fd.write(instr)
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fd.close()
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def test_file(s):
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ifn = f"../myTests/tmp/Top_inputs"
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ofn = f"../myTests/tmp/Top_outputs"
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randomInput(ifn)
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s.start(mode="task", ofn=ofn, ifn=ifn)
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pass
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def main():
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# Emitter.dumpVerilog(Emitter.dump(Emitter.emit(Top()), "Top.fir"))
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top_module_name = 'Top.v'
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dut_path = 'myTests/tmp/dut/'
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s = Simlite(top_module_name, dut_path, debug=True)
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# test_step(s)
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# test_task(s)
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test_file(s)
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s.close()
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if __name__ == '__main__':
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main()
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# randomInput(f"../myTests/tmp/Top_inputs")
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