forked from opendacs/PyHCL
23 lines
454 B
Python
23 lines
454 B
Python
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from pyhcl import *
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class MuxVec(Module):
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io = IO(
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i=Input(Bool),
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o=Output(Vec(4, Vec(8, U.w(32)))),
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)
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a = VecInit(VecInit(U.w(32)(i) for i in range(8)) for _ in range(4))
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b = VecInit(VecInit(U.w(32)(i) for i in range(7, -1, -1)) for _ in range(4))
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io.o <<= Mux(io.i, a, b)
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def main():
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f = Emitter.dump(Emitter.emit(MuxVec()), "muxVec.fir")
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Emitter.dumpVerilog(f)
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if __name__ == '__main__':
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main()
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