279 lines
7.4 KiB
C
279 lines
7.4 KiB
C
/* Copyright 2018 Canaan Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _DRIVER_GPIOHS_H
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#define _DRIVER_GPIOHS_H
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typedef enum _gpio_drive_mode
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{
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GPIO_DM_INPUT,
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GPIO_DM_INPUT_PULL_DOWN,
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GPIO_DM_INPUT_PULL_UP,
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GPIO_DM_OUTPUT,
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} gpio_drive_mode_t;
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typedef enum _gpio_pin_edge
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{
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GPIO_PE_NONE,
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GPIO_PE_FALLING,
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GPIO_PE_RISING,
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GPIO_PE_BOTH,
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GPIO_PE_LOW,
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GPIO_PE_HIGH = 8,
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} gpio_pin_edge_t;
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typedef enum _gpio_pin_value
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{
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GPIO_PV_LOW,
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GPIO_PV_HIGH
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} gpio_pin_value_t;
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/* clang-format off */
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/* Register address offsets */
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#define GPIOHS_INPUT_VAL (0x00)
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#define GPIOHS_INPUT_EN (0x04)
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#define GPIOHS_OUTPUT_EN (0x08)
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#define GPIOHS_OUTPUT_VAL (0x0C)
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#define GPIOHS_PULLUP_EN (0x10)
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#define GPIOHS_DRIVE (0x14)
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#define GPIOHS_RISE_IE (0x18)
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#define GPIOHS_RISE_IP (0x1C)
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#define GPIOHS_FALL_IE (0x20)
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#define GPIOHS_FALL_IP (0x24)
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#define GPIOHS_HIGH_IE (0x28)
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#define GPIOHS_HIGH_IP (0x2C)
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#define GPIOHS_LOW_IE (0x30)
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#define GPIOHS_LOW_IP (0x34)
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#define GPIOHS_IOF_EN (0x38)
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#define GPIOHS_IOF_SEL (0x3C)
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#define GPIOHS_OUTPUT_XOR (0x40)
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/* clang-format on */
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/**
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* @brief GPIO bits raw object
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*/
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typedef struct _gpiohs_raw
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{
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/* Address offset 0x00 */
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uint32 input_val;
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/* Address offset 0x04 */
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uint32 input_en;
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/* Address offset 0x08 */
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uint32 output_en;
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/* Address offset 0x0c */
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uint32 output_val;
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/* Address offset 0x10 */
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uint32 pullup_en;
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/* Address offset 0x14 */
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uint32 drive;
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/* Address offset 0x18 */
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uint32 rise_ie;
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/* Address offset 0x1c */
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uint32 rise_ip;
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/* Address offset 0x20 */
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uint32 fall_ie;
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/* Address offset 0x24 */
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uint32 fall_ip;
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/* Address offset 0x28 */
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uint32 high_ie;
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/* Address offset 0x2c */
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uint32 high_ip;
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/* Address offset 0x30 */
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uint32 low_ie;
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/* Address offset 0x34 */
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uint32 low_ip;
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/* Address offset 0x38 */
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uint32 iof_en;
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/* Address offset 0x3c */
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uint32 iof_sel;
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/* Address offset 0x40 */
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uint32 output_xor;
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} __attribute__((packed, aligned(4))) gpiohs_raw_t;
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/**
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* @brief GPIO bits object
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*/
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typedef struct _gpiohs_bits
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{
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uint32 b0 : 1;
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uint32 b1 : 1;
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uint32 b2 : 1;
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uint32 b3 : 1;
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uint32 b4 : 1;
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uint32 b5 : 1;
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uint32 b6 : 1;
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uint32 b7 : 1;
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uint32 b8 : 1;
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uint32 b9 : 1;
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uint32 b10 : 1;
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uint32 b11 : 1;
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uint32 b12 : 1;
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uint32 b13 : 1;
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uint32 b14 : 1;
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uint32 b15 : 1;
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uint32 b16 : 1;
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uint32 b17 : 1;
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uint32 b18 : 1;
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uint32 b19 : 1;
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uint32 b20 : 1;
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uint32 b21 : 1;
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uint32 b22 : 1;
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uint32 b23 : 1;
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uint32 b24 : 1;
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uint32 b25 : 1;
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uint32 b26 : 1;
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uint32 b27 : 1;
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uint32 b28 : 1;
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uint32 b29 : 1;
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uint32 b30 : 1;
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uint32 b31 : 1;
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} __attribute__((packed, aligned(4))) gpiohs_bits_t;
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/**
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* @brief GPIO bits multi access union
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*/
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typedef union _gpiohs_u32
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{
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/* 32x1 bit mode */
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uint32 u32[1];
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/* 16x2 bit mode */
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uint16 u16[2];
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/* 8x4 bit mode */
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uint8 u8[4];
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/* 1 bit mode */
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gpiohs_bits_t bits;
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} __attribute__((packed, aligned(4))) gpiohs_u32_t;
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/**
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* @brief GPIO object
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*
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* The GPIO controller is a peripheral device mapped in the
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* internal memory map, discoverable in the Configuration String.
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* It is responsible for low-level configuration of the actual
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* GPIO pads on the device (direction, pull up-enable, and drive
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* value), as well as selecting between various sources of the
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* controls for these signals. The GPIO controller allows seperate
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* configuration of each of N GPIO bits.
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*
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* Once the interrupt is pending, it will remain set until a 1 is
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* written to the *_ip register at that bit.
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*/
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typedef struct _gpiohs
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{
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/* Address offset 0x00, Input Values */
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gpiohs_u32_t input_val;
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/* Address offset 0x04, Input enable */
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gpiohs_u32_t input_en;
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/* Address offset 0x08, Output enable */
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gpiohs_u32_t output_en;
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/* Address offset 0x0c, Onput Values */
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gpiohs_u32_t output_val;
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/* Address offset 0x10, Internal Pull-Ups enable */
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gpiohs_u32_t pullup_en;
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/* Address offset 0x14, Drive Strength */
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gpiohs_u32_t drive;
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/* Address offset 0x18, Rise interrupt enable */
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gpiohs_u32_t rise_ie;
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/* Address offset 0x1c, Rise interrupt pending */
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gpiohs_u32_t rise_ip;
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/* Address offset 0x20, Fall interrupt enable */
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gpiohs_u32_t fall_ie;
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/* Address offset 0x24, Fall interrupt pending */
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gpiohs_u32_t fall_ip;
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/* Address offset 0x28, High interrupt enable */
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gpiohs_u32_t high_ie;
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/* Address offset 0x2c, High interrupt pending */
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gpiohs_u32_t high_ip;
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/* Address offset 0x30, Low interrupt enable */
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gpiohs_u32_t low_ie;
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/* Address offset 0x34, Low interrupt pending */
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gpiohs_u32_t low_ip;
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/* Address offset 0x38, HW I/O Function enable */
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gpiohs_u32_t iof_en;
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/* Address offset 0x3c, HW I/O Function select */
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gpiohs_u32_t iof_sel;
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/* Address offset 0x40, Output XOR (invert) */
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gpiohs_u32_t output_xor;
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} __attribute__((packed, aligned(4))) gpiohs_t;
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/**
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* @brief GPIO High-speed object instanse
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*/
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extern volatile gpiohs_t *const gpiohs;
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/**
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* @brief Set Gpiohs drive mode
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*
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* @param[in] pin Gpiohs pin
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* @param[in] mode Gpiohs pin drive mode
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*/
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void gpiohs_set_drive_mode(uint8 pin, gpio_drive_mode_t mode);
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/**
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* @brief Get Gpiohs pin value
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*
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* @param[in] pin Gpiohs pin
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* @return Pin value
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*
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* - GPIO_PV_Low Gpiohs pin low
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* - GPIO_PV_High Gpiohs pin high
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*/
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gpio_pin_value_t gpiohs_get_pin(uint8 pin);
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/**
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* @brief Set Gpiohs pin value
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*
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* @param[in] pin Gpiohs pin
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* @param[in] value Gpiohs pin value
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*/
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void gpiohs_set_pin(uint8 pin, gpio_pin_value_t value);
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/**
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* @brief Set Gpiohs pin edge for interrupt
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*
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* @param[in] pin Gpiohs pin
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* @param[in] edge Gpiohs pin edge type
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*/
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void gpiohs_set_pin_edge(uint8 pin, gpio_pin_edge_t edge);
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/**
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* @brief Set Gpiohs pin interrupt
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*
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* @param[in] pin Gpiohs pin
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* @param[in] priority Gpiohs pin interrupt priority
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* @param[in] func Gpiohs pin interrupt service routine
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*/
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void gpiohs_set_irq(uint8 pin, uint32 priority, void (*func)());
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/**
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* @brief Set Gpiohs pin interrupt
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*
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* @param[in] pin Gpiohs pin
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* @param[in] priority Gpiohs pin interrupt priority
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* @param[in] callback Gpiohs pin interrupt service routine
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* @param[in] ctx Gpiohs interrupt param
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*/
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//void gpiohs_irq_register(uint8 pin, uint32 priority, plic_irq_callback_t callback, void *ctx);
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/**
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* @brief Unregister Gpiohs pin interrupt
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*
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* @param[in] pin Gpiohs pin
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*/
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void gpiohs_irq_unregister(uint8 pin);
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#endif /* _DRIVER_GPIOHS_H */
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