fix timer interrupt
This commit is contained in:
parent
daa0d6efc2
commit
b06052d288
3
Makefile
3
Makefile
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@ -31,7 +31,6 @@ OBJS = \
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$K/kernelvec.o \
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$K/plic.o \
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$K/virtio_disk.o \
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$K/sbi.o \
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$K/timer.o \
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$K/test.o \
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@ -83,7 +82,7 @@ qemu: build
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image = $T/kernel.bin
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k210 = $T/k210.bin
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k210-serialport := /dev/ttyUSB0
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k210-serialport := /dev/ttyUSB1
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k210: build
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@riscv64-unknown-elf-objcopy $T/kernel --strip-all -O binary $(image)
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@ -20,6 +20,7 @@
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#include "riscv.h"
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#include "defs.h"
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#include "proc.h"
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#include "sbi.h"
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#define BACKSPACE 0x100
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#define C(x) ((x)-'@') // Control-x
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@ -23,15 +23,16 @@ void consoleintr(int);
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void consputc(int);
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// sbi.c
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void sbi_console_putchar(int ch);
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int sbi_console_getchar();
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void sbi_send_ipi(const unsigned long *hart_mask);
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void sbi_set_timer(uint64 stime_value);
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// void sbi_console_putchar(int ch);
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// int sbi_console_getchar();
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// void sbi_send_ipi(const unsigned long *hart_mask);
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// void sbi_set_timer(uint64 stime_value);
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// timer.c
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void timerinit();
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void supervisor_timer();
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void set_next_timeout();
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uint64 read_time();
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void timer_tick();
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// exec.c
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int exec(char*, char**);
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@ -0,0 +1,97 @@
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# 我们将会用一个宏来用循环保存寄存器。这是必要的设置
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.altmacro
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# 寄存器宽度对应的字节数
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.set REG_SIZE, 8
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# Context 的大小
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.set CONTEXT_SIZE, 34
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# 宏:将寄存器存到栈上
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.macro SAVE reg, offset
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sd \reg, \offset * REG_SIZE(sp)
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.endm
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# 宏:将寄存器从栈中取出
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.macro LOAD reg, offset
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ld \reg, \offset * REG_SIZE(sp)
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.endm
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# 宏:将 n 号寄存器保存在第 n 个位置
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.macro SAVE_N n
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SAVE x\n, n
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.endm
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# 宏:将 n 号寄存器从第 n 个位置取出
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.macro LOAD_N n
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LOAD x\n, n
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.endm
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.section .text
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.globl __interrupt
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# 进入中断
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# 保存 Context 并且进入 Rust 中的中断处理函数 interrupt::handler::handle_interrupt()
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__interrupt:
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# 因为线程当前的栈不一定可用,必须切换到内核栈来保存 Context 并进行中断流程
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# 因此,我们使用 sscratch 寄存器保存内核栈地址
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# 思考:sscratch 的值最初是在什么地方写入的?
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# 交换 sp 和 sscratch(切换到内核栈)
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csrrw sp, sscratch, sp
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# 在内核栈开辟 Context 的空间
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addi sp, sp, -CONTEXT_SIZE * REG_SIZE
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# 保存通用寄存器,除了 x0(固定为 0)
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SAVE x1, 1
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# 将本来的栈地址 sp(即 x2)保存
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csrr x1, sscratch
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SAVE x1, 2
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# 保存 x5 至 x31
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.set n, 5
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.rept 27
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SAVE_N %n
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.set n, n + 1
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.endr
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# 取出 CSR 并保存
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csrr t0, sstatus
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csrr t1, sepc
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SAVE t0, 32
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SAVE t1, 33
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# 调用 handle_interrupt,传入参数
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# context: &mut Context
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mv a0, sp
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# scause: Scause
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csrr a1, scause
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# stval: usize
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csrr a2, stval
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jal kerneltrap
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.globl __restore
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# 离开中断
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# 此时内核栈顶被推入了一个 Context,而 a0 指向它
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# 接下来从 Context 中恢复所有寄存器,并将 Context 出栈(用 sscratch 记录内核栈地址)
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# 最后跳转至恢复的 sepc 的位置
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__restore:
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# 从 a0 中读取 sp
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# 思考:a0 是在哪里被赋值的?(有两种情况)
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mv sp, a0
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# 恢复 CSR
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LOAD t0, 32
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LOAD t1, 33
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csrw sstatus, t0
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csrw sepc, t1
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# 将内核栈地址写入 sscratch
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addi t0, sp, CONTEXT_SIZE * REG_SIZE
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csrw sscratch, t0
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# 恢复通用寄存器
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LOAD x1, 1
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# 恢复 x5 至 x31
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.set n, 5
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.rept 27
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LOAD_N %n
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.set n, n + 1
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.endr
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# 恢复 sp(又名 x2)这里最后恢复是为了上面可以正常使用 LOAD 宏
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LOAD x2, 2
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sret
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@ -3,6 +3,7 @@
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#include "memlayout.h"
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#include "riscv.h"
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#include "defs.h"
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#include "sbi.h"
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volatile static int started = 0;
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@ -21,10 +22,10 @@ main(unsigned long hartid, unsigned long dtb_pa)
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kvminit(); // create kernel page table
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kvminithart(); // turn on paging
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test_kalloc();
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procinit();
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trapinit(); // trap vectors
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trapinithart(); // install kernel trap vector
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timerinit(); // set up timer interrupt handler
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procinit();
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// plicinit(); // set up interrupt controller
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// plicinithart(); // ask PLIC for device interrupts
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// binit(); // buffer cache
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@ -11,4 +11,4 @@
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#define NBUF (MAXOPBLOCKS*3) // size of disk block cache
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#define FSSIZE 1000 // size of file system in blocks
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#define MAXPATH 128 // maximum file path name
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#define INTERVAL 100 // timer interrupt interval
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#define INTERVAL (390000000 / 200) // timer interrupt interval
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@ -13,6 +13,7 @@
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#include "riscv.h"
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#include "defs.h"
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#include "proc.h"
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#include "sbi.h"
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volatile int panicked = 0;
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@ -253,7 +253,8 @@ static inline uint64
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r_time()
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{
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uint64 x;
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asm volatile("csrr %0, time" : "=r" (x) );
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// asm volatile("csrr %0, time" : "=r" (x) );
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asm volatile("rdtime %0" : "=r" (x) );
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return x;
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}
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96
kernel/sbi.h
96
kernel/sbi.h
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@ -1,5 +1,93 @@
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// SBI Call Head file
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Regents of the University of California
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*/
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void sbi_console_putchar(int ch);
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int sbi_console_getchar();
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void sbi_send_ipi(const unsigned long *hart_mask);
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#ifndef _ASM_RISCV_SBI_H
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#define _ASM_RISCV_SBI_H
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#include "types.h"
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#define SBI_SET_TIMER 0
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#define SBI_CONSOLE_PUTCHAR 1
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#define SBI_CONSOLE_GETCHAR 2
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#define SBI_CLEAR_IPI 3
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#define SBI_SEND_IPI 4
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#define SBI_REMOTE_FENCE_I 5
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#define SBI_REMOTE_SFENCE_VMA 6
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#define SBI_REMOTE_SFENCE_VMA_ASID 7
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#define SBI_SHUTDOWN 8
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#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({ \
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register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \
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register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \
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register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \
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register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3); \
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register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \
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asm volatile ("ecall" \
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: "+r" (a0) \
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: "r" (a1), "r" (a2), "r" (a3), "r" (a7) \
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: "memory"); \
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a0; \
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})
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/* Lazy implementations until SBI is finalized */
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#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0, 0)
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#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0, 0)
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#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0, 0)
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#define SBI_CALL_3(which, arg0, arg1, arg2) \
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SBI_CALL(which, arg0, arg1, arg2, 0)
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#define SBI_CALL_4(which, arg0, arg1, arg2, arg3) \
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SBI_CALL(which, arg0, arg1, arg2, arg3)
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static inline void sbi_console_putchar(int ch)
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{
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SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch);
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}
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static inline int sbi_console_getchar(void)
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{
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return SBI_CALL_0(SBI_CONSOLE_GETCHAR);
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}
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static inline void sbi_set_timer(uint64 stime_value)
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{
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SBI_CALL_1(SBI_SET_TIMER, stime_value);
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}
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static inline void sbi_shutdown(void)
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{
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SBI_CALL_0(SBI_SHUTDOWN);
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}
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static inline void sbi_clear_ipi(void)
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{
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SBI_CALL_0(SBI_CLEAR_IPI);
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}
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static inline void sbi_send_ipi(const unsigned long *hart_mask)
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{
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SBI_CALL_1(SBI_SEND_IPI, hart_mask);
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}
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static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
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{
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SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask);
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}
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static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
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unsigned long start,
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unsigned long size)
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{
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SBI_CALL_3(SBI_REMOTE_SFENCE_VMA, hart_mask, start, size);
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}
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static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
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unsigned long start,
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unsigned long size,
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unsigned long asid)
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{
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SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid);
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}
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#endif
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@ -4,6 +4,7 @@
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#include "param.h"
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#include "riscv.h"
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#include "defs.h"
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#include "sbi.h"
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static int tick = 0;
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void timerinit() {
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void set_next_timeout() {
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printf("[Timer]read_time: %d\n", r_time());
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// printf("[Timer]read_time: %d\n", read_time());
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sbi_set_timer(r_time() + INTERVAL);
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}
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uint64 read_time() {
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uint64 *mtime = (uint64 *)0xffffffff0200bff8;
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return *(mtime);
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}
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void timer_tick() {
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printf("[Timer]tick\n");
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set_next_timeout();
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@ -13,6 +13,7 @@ extern char trampoline[], uservec[], userret[];
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// in kernelvec.S, calls kerneltrap().
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void kernelvec();
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void __interrupt();
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extern int devintr();
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@ -28,6 +29,7 @@ void
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trapinithart(void)
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{
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w_stvec((uint64)kernelvec);
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w_sstatus(r_sstatus() | SSTATUS_SIE);
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w_sie(r_sie() | SIE_SEIE | SIE_SSIE);
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printf("trapinithart\n");
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}
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panic("kerneltrap");
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}
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printf("which_dev: %d\n", which_dev);
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// give up the CPU if this is a timer interrupt.
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if(which_dev == 2 && myproc() != 0 && myproc()->state == RUNNING) {
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supervisor_timer();
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yield();
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}
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// the yield() may have caused some traps to occur,
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// so restore trap registers for use by kernelvec.S's sepc instruction.
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w_sepc(sepc);
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@ -7,4 +7,5 @@ typedef unsigned short uint16;
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typedef unsigned int uint32;
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typedef unsigned long uint64;
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typedef unsigned long uintptr_t;
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typedef uint64 pde_t;
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