221 lines
7.6 KiB
C
221 lines
7.6 KiB
C
#ifndef _RISCV_H_
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#define _RISCV_H_
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#include "util/types.h"
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#include "config.h"
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// fields of mstatus, the Machine mode Status register
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#define MSTATUS_MPP_MASK (3L << 11) // previous mode mask
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#define MSTATUS_MPP_M (3L << 11) // machine mode (m-mode)
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#define MSTATUS_MPP_S (1L << 11) // supervisor mode (s-mode)
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#define MSTATUS_MPP_U (0L << 11) // user mode (u-mode)
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#define MSTATUS_MIE (1L << 3) // machine-mode interrupt enable
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#define MSTATUS_MPIE (1L << 7) // preserve MIE bit
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// values of mcause, the Machine Cause register
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#define IRQ_S_EXT 9 // s-mode external interrupt
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#define IRQ_S_TIMER 5 // s-mode timer interrupt
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#define IRQ_S_SOFT 1 // s-mode software interrupt
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#define IRQ_M_SOFT 3 // m-mode software interrupt
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// fields of mip, the Machine Interrupt Pending register
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#define MIP_SEIP (1 << IRQ_S_EXT) // s-mode external interrupt pending
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#define MIP_SSIP (1 << IRQ_S_SOFT) // s-mode software interrupt pending
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#define MIP_STIP (1 << IRQ_S_TIMER) // s-mode timer interrupt pending
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#define MIP_MSIP (1 << IRQ_M_SOFT) // m-mode software interrupt pending
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// pysical memory protection choices
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#define PMP_R 0x01
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#define PMP_W 0x02
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#define PMP_X 0x04
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#define PMP_A 0x18
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#define PMP_L 0x80
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#define PMP_SHIFT 2
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#define PMP_TOR 0x08
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#define PMP_NA4 0x10
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#define PMP_NAPOT 0x18
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// exceptions
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#define CAUSE_MISALIGNED_FETCH 0x0 // Instruction address misaligned
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#define CAUSE_FETCH_ACCESS 0x1 // Instruction access fault
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#define CAUSE_ILLEGAL_INSTRUCTION 0x2 // Illegal Instruction
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#define CAUSE_BREAKPOINT 0x3 // Breakpoint
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#define CAUSE_MISALIGNED_LOAD 0x4 // Load address misaligned
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#define CAUSE_LOAD_ACCESS 0x5 // Load access fault
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#define CAUSE_MISALIGNED_STORE 0x6 // Store/AMO address misaligned
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#define CAUSE_STORE_ACCESS 0x7 // Store/AMO access fault
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#define CAUSE_USER_ECALL 0x8 // Environment call from U-mode
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#define CAUSE_SUPERVISOR_ECALL 0x9 // Environment call from S-mode
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#define CAUSE_MACHINE_ECALL 0xb // Environment call from M-mode
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#define CAUSE_FETCH_PAGE_FAULT 0xc // Instruction page fault
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#define CAUSE_LOAD_PAGE_FAULT 0xd // Load page fault
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#define CAUSE_STORE_PAGE_FAULT 0xf // Store/AMO page fault
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// irqs (interrupts)
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#define CAUSE_MTIMER 0x8000000000000007
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#define CAUSE_MTIMER_S_TRAP 0x8000000000000001
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//Supervisor interrupt-pending register
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#define SIP_SSIP (1L << 1)
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// core local interruptor (CLINT), which contains the timer.
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#define CLINT 0x2000000L
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#define CLINT_MTIMECMP(hartid) (CLINT + 0x4000 + 8 * (hartid))
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#define CLINT_MTIME (CLINT + 0xBFF8) // cycles since boot.
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// fields of sstatus, the Supervisor mode Status register
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#define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User
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#define SSTATUS_SPIE (1L << 5) // Supervisor Previous Interrupt Enable
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#define SSTATUS_UPIE (1L << 4) // User Previous Interrupt Enable
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#define SSTATUS_SIE (1L << 1) // Supervisor Interrupt Enable
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#define SSTATUS_UIE (1L << 0) // User Interrupt Enable
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#define SSTATUS_SUM 0x00040000
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#define SSTATUS_FS 0x00006000
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// Supervisor Interrupt Enable
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#define SIE_SEIE (1L << 9) // external
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#define SIE_STIE (1L << 5) // timer
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#define SIE_SSIE (1L << 1) // software
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// Machine-mode Interrupt Enable
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#define MIE_MEIE (1L << 11) // external
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#define MIE_MTIE (1L << 7) // timer
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#define MIE_MSIE (1L << 3) // software
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#define read_const_csr(reg) \
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({ \
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unsigned long __tmp; \
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asm("csrr %0, " #reg : "=r"(__tmp)); \
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__tmp; \
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})
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static inline int supports_extension(char ext) {
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return read_const_csr(misa) & (1 << (ext - 'A'));
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}
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#define read_csr(reg) \
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({ \
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unsigned long __tmp; \
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asm volatile("csrr %0, " #reg : "=r"(__tmp)); \
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__tmp; \
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})
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#define write_csr(reg, val) ({ asm volatile("csrw " #reg ", %0" ::"rK"(val)); })
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#define swap_csr(reg, val) \
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({ \
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unsigned long __tmp; \
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asm volatile("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \
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__tmp; \
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})
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#define set_csr(reg, bit) \
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({ \
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unsigned long __tmp; \
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asm volatile("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
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__tmp; \
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})
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// enable device interrupts
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static inline void intr_on(void) { write_csr(sstatus, read_csr(sstatus) | SSTATUS_SIE); }
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// disable device interrupts
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static inline void intr_off(void) { write_csr(sstatus, read_csr(sstatus) & ~SSTATUS_SIE); }
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// are device interrupts enabled?
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static inline int is_intr_enable(void) {
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// uint64 x = r_sstatus();
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uint64 x = read_csr(sstatus);
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return (x & SSTATUS_SIE) != 0;
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}
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// read sp, the stack pointer
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static inline uint64 read_sp(void) {
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uint64 x;
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asm volatile("mv %0, sp" : "=r"(x));
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return x;
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}
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// read tp, the thread pointer, holding hartid (core number), the index into cpus[].
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static inline uint64 read_tp(void) {
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uint64 x;
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asm volatile("mv %0, tp" : "=r"(x));
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return x;
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}
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// write tp, the thread pointer, holding hartid (core number), the index into cpus[].
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static inline void write_tp(uint64 x) { asm volatile("mv tp, %0" : : "r"(x)); }
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static inline void flush_tlb(void) { asm volatile("sfence.vma zero, zero"); }
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#define PGSIZE 4096 // bytes per page
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#define PGSHIFT 12 // bits of offset within a page
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// use riscv's sv39 page table scheme.
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#define SATP_SV39 (8L << 60)
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#define MAKE_SATP(pagetable) (SATP_SV39 | (((uint64)pagetable) >> 12))
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#define PTE_V (1L << 0) // valid
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#define PTE_R (1L << 1)
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#define PTE_W (1L << 2)
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#define PTE_X (1L << 3)
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#define PTE_U (1L << 4) // 1 -> user can access
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#define PTE_G (1L << 5) // Global
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#define PTE_A (1L << 6) // Accessed
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#define PTE_D (1L << 7) // Dirty
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// shift a physical address to the right place for a PTE.
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#define PA2PTE(pa) ((((uint64)pa) >> 12) << 10)
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#define PTE2PA(pte) (((pte) >> 10) << 12)
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#define PTE_FLAGS(pte) ((pte)&0x3FF)
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// extract the three 9-bit page table indices from a virtual address.
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#define PXMASK 0x1FF // 9 bits
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#define PXSHIFT(level) (PGSHIFT + (9 * (level)))
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#define PX(level, va) ((((uint64)(va)) >> PXSHIFT(level)) & PXMASK)
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// one beyond the highest possible virtual address.
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// MAXVA is actually one bit less than the max allowed by
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// Sv39, to avoid having to sign-extend virtual addresses
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// that have the high bit set.
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#define MAXVA (1L << (9 + 9 + 9 + 12 - 1))
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typedef uint64 pte_t;
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typedef uint64 *pagetable_t; // 512 PTEs
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typedef struct riscv_regs {
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/* 0 */ uint64 ra;
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/* 8 */ uint64 sp;
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/* 16 */ uint64 gp;
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/* 24 */ uint64 tp;
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/* 32 */ uint64 t0;
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/* 40 */ uint64 t1;
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/* 48 */ uint64 t2;
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/* 56 */ uint64 s0;
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/* 64 */ uint64 s1;
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/* 72 */ uint64 a0;
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/* 80 */ uint64 a1;
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/* 88 */ uint64 a2;
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/* 96 */ uint64 a3;
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/* 104 */ uint64 a4;
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/* 112 */ uint64 a5;
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/* 120 */ uint64 a6;
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/* 128 */ uint64 a7;
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/* 136 */ uint64 s2;
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/* 144 */ uint64 s3;
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/* 152 */ uint64 s4;
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/* 160 */ uint64 s5;
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/* 168 */ uint64 s6;
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/* 176 */ uint64 s7;
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/* 184 */ uint64 s8;
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/* 192 */ uint64 s9;
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/* 196 */ uint64 s10;
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/* 208 */ uint64 s11;
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/* 216 */ uint64 t3;
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/* 224 */ uint64 t4;
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/* 232 */ uint64 t5;
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/* 240 */ uint64 t6;
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}riscv_regs;
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#endif
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