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lab1_1_sys
...
lab1_2_exc
Author | SHA1 | Date |
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Zhiyuan Shao | 8c64512cab |
2
Makefile
2
Makefile
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@ -69,8 +69,8 @@ USER_CPPS := user/*.c
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USER_CPPS := $(wildcard $(USER_CPPS))
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USER_CPPS := $(wildcard $(USER_CPPS))
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USER_OBJS := $(addprefix $(OBJ_DIR)/, $(patsubst %.c,%.o,$(USER_CPPS)))
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USER_OBJS := $(addprefix $(OBJ_DIR)/, $(patsubst %.c,%.o,$(USER_CPPS)))
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USER_TARGET := $(OBJ_DIR)/app_helloworld
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USER_TARGET := $(OBJ_DIR)/app_illegal_instruction
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#------------------------targets------------------------
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#------------------------targets------------------------
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$(OBJ_DIR):
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$(OBJ_DIR):
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@-mkdir -p $(OBJ_DIR)
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@-mkdir -p $(OBJ_DIR)
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@ -16,11 +16,15 @@ __attribute__((aligned(16))) char stack0[4096 * NCPU];
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// sstart is the supervisor state entry point
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// sstart is the supervisor state entry point
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extern void s_start(); // defined in kernel/kernel.c
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extern void s_start(); // defined in kernel/kernel.c
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// M-mode trap entry point
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extern void mtrapvec();
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// htif is defined in kernel/machine/spike_htif.c, marks the availability of HTIF
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// htif is defined in kernel/machine/spike_htif.c, marks the availability of HTIF
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extern uint64 htif;
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extern uint64 htif;
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// g_mem_size is defined in kernel/machine/spike_memory.c, size of the emulated memory
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// g_mem_size is defined in kernel/machine/spike_memory.c, size of the emulated memory
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extern uint64 g_mem_size;
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extern uint64 g_mem_size;
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// g_itrframe is used for saving registers when interrupt hapens in M mode
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struct riscv_regs g_itrframe;
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//
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//
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// get the information of HTIF (calling interface) and the emulated memory by
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// get the information of HTIF (calling interface) and the emulated memory by
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@ -73,12 +77,18 @@ void m_start(uintptr_t hartid, uintptr_t dtb) {
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// init HTIF (Host-Target InterFace) and memory by using the Device Table Blob (DTB)
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// init HTIF (Host-Target InterFace) and memory by using the Device Table Blob (DTB)
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init_dtb(dtb);
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init_dtb(dtb);
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// save the address of frame for interrupt in M mode to csr "mscratch".
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write_csr(mscratch, &g_itrframe);
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// set previous privilege mode to S (Supervisor), and will enter S mode after 'mret'
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// set previous privilege mode to S (Supervisor), and will enter S mode after 'mret'
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write_csr(mstatus, ((read_csr(mstatus) & ~MSTATUS_MPP_MASK) | MSTATUS_MPP_S));
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write_csr(mstatus, ((read_csr(mstatus) & ~MSTATUS_MPP_MASK) | MSTATUS_MPP_S));
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// set M Exception Program Counter to sstart, for mret (requires gcc -mcmodel=medany)
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// set M Exception Program Counter to sstart, for mret (requires gcc -mcmodel=medany)
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write_csr(mepc, (uint64)s_start);
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write_csr(mepc, (uint64)s_start);
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// setup trap handling vector
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write_csr(mtvec, (uint64)mtrapvec);
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// delegate all interrupts and exceptions to supervisor mode.
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// delegate all interrupts and exceptions to supervisor mode.
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delegate_traps();
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delegate_traps();
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@ -0,0 +1,51 @@
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#include "kernel/riscv.h"
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#include "kernel/process.h"
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#include "spike_interface/spike_utils.h"
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static void handle_instruction_access_fault() { panic("Instruction access fault!"); }
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static void handle_load_access_fault() { panic("Load access fault!"); }
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static void handle_store_access_fault() { panic("Store/AMO access fault!"); }
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static void handle_illegal_instruction() { panic("Illegal instruction!"); }
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static void handle_misaligned_load() { panic("Misaligned Load!"); }
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static void handle_misaligned_store() { panic("Misaligned AMO!"); }
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//
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// handle_mtrap calls cooresponding functions to handle an exception of a given type.
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//
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void handle_mtrap() {
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uint64 mcause = read_csr(mcause);
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switch (mcause) {
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case CAUSE_FETCH_ACCESS:
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handle_instruction_access_fault();
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break;
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case CAUSE_LOAD_ACCESS:
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handle_load_access_fault();
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case CAUSE_STORE_ACCESS:
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handle_store_access_fault();
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break;
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case CAUSE_ILLEGAL_INSTRUCTION:
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// TODO (lab1_2): call handle_illegal_instruction to implement illegal instruction
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// interception, and finish lab1_2.
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panic( "call handle_illegal_instruction to accomplish illegal instruction interception for lab1_2.\n" );
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break;
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case CAUSE_MISALIGNED_LOAD:
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handle_misaligned_load();
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break;
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case CAUSE_MISALIGNED_STORE:
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handle_misaligned_store();
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break;
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default:
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sprint("machine trap(): unexpected mscause %p\n", mcause);
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sprint(" mepc=%p mtval=%p\n", read_csr(mepc), read_csr(mtval));
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panic( "unexpected exception happened in M-mode.\n" );
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break;
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}
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}
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@ -0,0 +1,38 @@
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#include "util/load_store.S"
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#
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# M-mode trap entry point
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#
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.globl mtrapvec
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.align 4
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mtrapvec:
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# swap a0 and mscratch
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# so that a0 points to interrupt frame
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csrrw a0, mscratch, a0
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# save the registers in interrupt frame
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addi t6, a0, 0
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store_all_registers
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# save the user a0 in itrframe->a0
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csrr t0, mscratch
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sd t0, 72(a0)
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# use stack0 for sp
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la sp, stack0
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li a3, 4096
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csrr a4, mhartid
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addi a4, a4, 1
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mul a3, a3, a4
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add sp, sp, a3
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// save the address of interrupt frame in the csr "mscratch"
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csrw mscratch, a0
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call handle_mtrap
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// restore all registers
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csrr t6, mscratch
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restore_all_registers
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mret
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@ -1,17 +0,0 @@
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/*
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* Below is the given application for lab1_1.
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*
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* You can build this app (as well as our PKE OS kernel) by command:
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* $ make
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*
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* Or run this app (with the support from PKE OS kernel) by command:
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* $ make run
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*/
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#include "user_lib.h"
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int main(void) {
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printu("Hello world!\n");
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exit(0);
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}
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@ -0,0 +1,15 @@
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/*
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* Below is the given application for lab1_2.
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* This app attempts to issue M-mode instruction in U-mode, and consequently raises an exception.
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*/
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#include "user_lib.h"
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#include "util/types.h"
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int main(void) {
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printu("Going to hack the system by running privilege instructions.\n");
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// we are now in U(user)-mode, but the "csrw" instruction requires M-mode privilege.
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// Attempting to execute such instruction will raise illegal instruction exception.
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asm volatile("csrw sscratch, 0");
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exit(0);
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}
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