fpga-pynq/.gitignore

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*.log
*.jou
*.Xil
zedboard/zedboard_rocketchip
zedboard/src/tcl/zedboard_rocketchip.tcl
zedboard/src/tcl/make_bitstream.tcl
zedboard/src/verilog/rocketchip_wrapper.v
zedboard/deliver_output
zedboard/soft_build
zybo/zybo_rocketchip
zybo/src/tcl/zybo_rocketchip.tcl
zybo/src/tcl/make_bitstream.tcl
zybo/src/verilog/rocketchip_wrapper.v
zybo/deliver_output
zybo/soft_build
zc706/zc706_rocketchip
zc706/src/tcl/zc706_rocketchip.tcl
zc706/src/tcl/make_bitstream.tcl
zc706/src/verilog/rocketchip_wrapper.v
zc706/deliver_output
zc706/soft_build