1e9c73ffc6
update generated bitstreams
2018-04-18 17:51:13 -07:00
4556425d58
upgrade to latest RocketChip
...
* Scala updates to 2.11.12
* Bootrom code moved to testchipip
* Makefrag for testchipip blackboxes moved to testchipip
* Added support for block device
2018-04-18 17:49:15 -07:00
9a0b82d0c4
update FPGA images
2016-10-28 13:52:38 -07:00
42959c7514
get rid of generated verilog files
2016-10-07 16:57:01 -07:00
bf036fb956
start implementing alternate adapter interface
2016-09-29 12:44:47 -07:00
98669e298f
update to post- cake pattern refactor rocketchip
2016-09-22 12:04:51 -07:00
6c06d97cb1
Conform to new rocketchip generator. Fix adapter concat bugs
...
This brings fpga-zynq up to sync with Henry's changes to rocket-chip
generation utilities. It also fixes a silly bug that assumed constant
field orderings when toBits-ing an aggregate.
2016-09-08 16:48:59 -07:00
dc3a871e65
Bump zedboard, zc706 image submodules
2016-08-23 14:13:33 -07:00
66093b4a32
Upgrade projects to version 2016.2
2016-08-18 12:43:19 -07:00
33dcf3efa7
Makefile bug fixes, generator config lookup enhancement
2016-08-17 14:10:53 -07:00
9bfaca46a0
Update readme, enable config lookup from multiple projects
2016-08-12 16:39:18 -07:00
3ca6ba6f94
Add a top level zynq project and link against RC
2016-08-10 18:02:59 -07:00
0b3237681b
Add DTM driver and new zynq main
...
Test changes on other platforms + cleanup
2016-08-10 18:02:54 -07:00
cfc0a61f30
move AXI to HTIF conversion to Chisel-generated module
2016-02-19 13:53:12 -08:00
7308fd0bcd
new 2015.4 images for zc706
2016-01-06 09:37:36 -08:00
4f13b7fd39
port zc706 block design to 2015.4
2016-01-06 09:37:05 -08:00
5752e4e1bb
newest rocket chip verilog to zc706
2016-01-05 15:43:48 -08:00
3fe061bb49
replace MemIO interface with multi-channel AXI interface
2015-11-05 10:45:48 -08:00
eb82eb8b80
new ramdisk including addition of bbl
2015-08-21 14:41:37 -07:00
824b75bd18
zc706 using updated rocket chip
2015-08-21 14:15:17 -07:00
02cd99252e
update zc706 for vivado 2015.2
2015-07-16 13:44:47 -07:00
ee630a4481
Constrain internal clock input on ZC706
2015-06-05 12:00:49 -07:00
b286dd0f43
bump pre-built images for recent updates
2015-01-07 16:17:58 -08:00
1ab1a2ecef
updates to handle vivado 2014.4
2015-01-07 16:17:56 -08:00
628a357451
verilog from newest rocket-chip and chisel
2015-01-07 16:17:54 -08:00
19243ebb15
renaming CHISEL_CONFIG to CONFIG
...
this way it can be easily overriden in the same way as rocket-chip
2014-10-01 13:48:06 -07:00
c98d15296f
bump zc706 and zybo images repos to use new uramdisk
2014-09-26 11:46:49 -07:00
93f19aa337
bump zc706, zybo images
2014-09-24 18:33:33 -07:00
09a7ceaf25
add zc706 submodule, bump zybo
2014-09-24 13:32:56 -07:00
94cf24b2dd
newest verilog from newest chisel
2014-09-23 17:30:39 -07:00
97355d0e50
properly use new chisel configs
2014-09-23 17:02:48 -07:00
e7b0249cba
add dtb compilation target: make arm-dtb
2014-09-21 18:30:41 -07:00
f1071df249
add make targets for arm-linux and arm-uboot
2014-09-21 18:22:42 -07:00
e38729ea18
add common linux-xlnx submodule + zc706/zybo dts files
2014-09-21 16:34:28 -07:00
6c8a4581f6
modify zybo u-boot config to support upstream u-boot-xlnx instead of Digilent repo, add u-boot-xlnx common submodule
2014-09-21 16:12:15 -07:00
0844d0bc23
Working 2014.2 bd tcl for zc706
...
* tested with
57ee2dcc1f/zc706/src/verilog/Top.DefaultFPGAConfig.v
2014-09-21 14:32:14 -07:00
0cc12a9a95
support for using chisel configs and calling into rocket-chip to generate new verilog
2014-09-19 18:02:35 -07:00
5524f27c2c
add zedboard board model and simplify replacement names
2014-09-13 11:19:58 -07:00
d4ca714501
support zc706 differential clock (still supports zedboard/zynq single ended clock)
2014-09-13 00:36:40 -07:00
913cc39c9a
separate common board name and official board name required by vivado
2014-09-12 21:44:36 -07:00
57ee2dcc1f
start zc706
2014-09-12 20:58:59 -07:00
Howard Mao