make submodule building more extensible
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parent
42959c7514
commit
f6978c40e0
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@ -2,11 +2,11 @@
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JOBS = 16
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ROCKET_DIR ?= $(base_dir)/rocket-chip
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TESTCHIP_DIR ?= $(base_dir)/testchipip
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TOP_MODULE_PROJECT ?= zynq
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TOP_MODULE ?= Top
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CFG_PROJECT ?= $(TOP_MODULE_PROJECT)
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CONFIG ?= ZynqConfig
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EXTRA_PACKAGES=testchipip
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base_dir = $(abspath ..)
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common = $(base_dir)/common
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@ -16,7 +16,7 @@ SHELL := /bin/bash
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bootrom_img = $(common)/bootrom/bootrom.img
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rocketchip_stamp = $(common)/lib/rocketchip.stamp
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testchipip_stamp = $(common)/lib/testchipip.stamp
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extra_stamps = $(addprefix $(common)/lib/,$(addsuffix .stamp,$(EXTRA_PACKAGES)))
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ifneq ($(BOARD_MODEL),)
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insert_board = s/\# REPLACE FOR OFFICIAL BOARD NAME/set_property "board_part" "$(BOARD_MODEL)"/g
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@ -71,13 +71,14 @@ $(rocketchip_stamp): $(call lookup_scala_srcs, $(ROCKET_DIR))
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cp $(ROCKET_DIR)/target/pack/lib/* $(common)/lib
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touch $(rocketchip_stamp)
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$(testchipip_stamp): $(call lookup_scala_srcs, $(TESTCHIP_DIR)) $(rocketchip_stamp)
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ln -sf $(common)/lib $(TESTCHIP_DIR)/lib
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cd $(TESTCHIP_DIR) && $(SBT) package
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cp $(TESTCHIP_DIR)/target/scala-2.11/*.jar $(common)/lib
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touch $(testchipip_stamp)
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$(common)/%.stamp: $(call lookup_scala_srcs, %) $(rocketchip_stamp)
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rm -f $(base_dir)/$(patsubst %.stamp,%,$(notdir $@))/lib
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ln -s $(common)/lib $(base_dir)/$(patsubst %.stamp,%,$(notdir $@))/lib
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cd $(base_dir)/$(patsubst %.stamp,%,$(notdir $@)) && $(SBT) package
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cp $(base_dir)/$(patsubst %.stamp,%,$(notdir $@))/target/scala-2.11/*.jar $(common)/lib
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touch $@
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$(common_build)/$(TOP_MODULE).$(CONFIG).fir: $(rocketchip_stamp) $(testchipip_stamp) $(bootrom_img) $(call lookup_scala_srcs,$(common))
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$(common_build)/$(TOP_MODULE).$(CONFIG).fir: $(rocketchip_stamp) $(extra_stamps) $(bootrom_img) $(call lookup_scala_srcs,$(common))
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mkdir -p $(@D)
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cd $(common) && $(SBT) "run $(CHISEL_ARGS) $(TOP_MODULE_PROJECT) $(TOP_MODULE) $(CFG_PROJECT) $(CONFIG)"
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@ -13,10 +13,10 @@ include ../common/Makefrag
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sim_vsrcs = \
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src/verilog/$(TOP_MODULE).$(CONFIG).v \
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$(common)/vsrc/TestDriver.v \
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$(TESTCHIP_DIR)/vsrc/SimSerial.v
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$(base_dir)/testchipip/vsrc/SimSerial.v
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sim_csrcs = \
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$(TESTCHIP_DIR)/csrc/SimSerial.cc
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$(base_dir)/testchipip/csrc/SimSerial.cc
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VCS = vcs -full64
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