Update readme, enable config lookup from multiple projects

README.md

@@ -123,14 +123,20 @@ _Note:_ If you like, you can have fpga-zynq and rocket-chip have any relative po
 
 #### <a name="configRC"></a> Configuring Rocket Chip
 
-The verilog for the rocket chip is generated by [Chisel](https://chisel.eecs.berkeley.edu) and thus is not intended to be edited by humans. To change the rocket chip, you should modify its chisel code and regenerate the verilog. For information on changing rocket chip, consult its [documentation](https://github.com/ucb-bar/rocket-chip).
+The verilog for the rocket chip is generated by [Chisel](https://chisel.eecs.berkeley.edu) and thus is not intended to be edited by humans. This project instantiates rocket chip as module larger top level chisel project, that includes an adapter to interface the ARM core with rocket chip's debug module. To change rocket chip, you should modify its chisel code and repack the libraries (which drops the updated jars in /common/lib) like so:
+
+    $ make pack-rocket
+
+This places a set of static jars in /common/lib, including rocketchip, chisel3, and firrtl.
+
+The configuration used to generate the rocket chip comes from the (`CONFIG_PROJECT`, `CONFIG`) environment variables. If `CONFIG` isn't set by the environment, it is taken from the `Makefile` for the current board. For this example, we use the Zybo which has a default configuration of `DefaultFPGASmallConfig`.
+
 
-The configuration used to generate the rocket chip comes from the `CONFIG` environment variable. If `CONFIG` isn't set by the environment, it is taken from the `Makefile` for the current board. For this example, we use the Zybo which has a default configuration of `DefaultFPGASmallConfig`.
 
 #### <a name="genRC"></a> Generating Verilog for Rocket Chip
 _Requires: JVM that can run Scala_
 
-Enter into the directory for your board (current options are `zybo`, `zedboard`, and `zc706`). After making changes within `rocket-chip`, to run the rocket chip generator and copy the newly generated verilog back into the board's source, run:
+Enter into the directory for your board (current options are `zybo`, `zedboard`, and `zc706`). After making changes within `rocket-chip` and/or `common/src/main/scala`, to run the rocket chip generator and copy the newly generated verilog back into the board's source, run:
 
      $ make rocket
 
@@ -138,7 +144,12 @@ You can also explicitly set the `CONFIG` variable from the command-line (can do
 
      $ make rocket CONFIG=MyFPGAConfig
 
-Different configurations can coexist, since they will generate different  verilog filenames (e.g. _Top.MyFPGAConfig.v_).
+By default this will look up a configuration specified in the rocket chip library. You may define a custom one without recompiling rocketchip, by defining in the zynq chisel sources at `common/src/main/scala`, and instead calling:
+
+     $ make rocket CONFIG_PROJECT=zynq CONFIG=MyCustomZynqConfig
+
+The generator will instead look for the configuration definition in the local project instead of the rocket chip library.
+
 
 #### <a name="projRC"></a> Generating Project for Configuration
 To generate a Vivado project specific to the board and the configuration (one project per configuration):
@@ -445,14 +456,11 @@ The SD card is used by the board to configure the FPGA and boot up the ARM core.
 
 ###F) <a name="fesvr"></a> Building fesvr-zynq
 
-The source code for the fesvr-zynq binary is in the [riscv-fesvr repo](http://github.com/riscv/riscv-fesvr). Before building, make sure the 2015.4 version of settings64.sh is sourced. To build the riscv-fesvr binary for Linux ARM target (to run on Zynq board), type:
+The [riscv-fesvr repo](http://github.com/riscv/riscv-fesvr) provides against which the zynq-fesvr is linked. Additionally, `common/csrc` includes source for main, and a simple driver, which hands off debug module requests and reponses between the ARM core and rocket chip. Before building, make sure the 2015.4 version of settings64.sh is sourced. To build the riscv-fesvr binary for Linux ARM target (to run on Zynq board), type:
 
-    $ mkdir build
+    $ make fesvr-zynq
-    $ cd build
-    $ ../configure --host=arm-xilinx-linux-gnueabi
-    $ make
 
-from the riscv-fesvr/build directory and make sure you have the Xilinx SDK in your PATH. When installing fesvr-zynq, don't forget to copy the library as well (`build/libfesvr.so` to `/usr/local/lib` on the board).
+and make sure you have the Xilinx SDK in your PATH. When installing fesvr-zynq, don't forget to copy the library as well (`common/build/libfesvr.so` to `/usr/local/lib` on the board).
 
 
 ###G) <a name="zybotools"></a> Building riscv-tools for Zybo
@@ -478,6 +486,7 @@ In addition to those that [contributed](https://github.com/ucb-bar/rocket-chip#c
 
 - Rimas Avizienis
 - Jonathan Bachrach
+- David Biancolin
 - Scott Beamer
 - Sagar Karandikar
 - Deborah Soung

common/Makefrag

@@ -28,7 +28,7 @@ SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKET_DIR)/sbt-launch.jar
 FIRRTL_JAR ?= $(ROCKET_DIR)/firrtl/utils/bin/firrtl.jar
 FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver
 
-$(FIRRTL_JAR): $(@shell find $(ROCKET_DIR)/firrtl/src/main/scala -iname "*.scala")
+$(FIRRTL_JAR): $(shell find $(ROCKET_DIR)/firrtl/src/main/scala -iname "*.scala" 2> /dev/null)
 	$(MAKE) -C $(ROCKET_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKET_DIR)/firrtl build-scala
 
 CHISEL_ARGS := --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(common_build)
@@ -52,21 +52,21 @@ $(common)/bootrom:
 	ln -s $(ROCKET_DIR)/bootrom $(common)/bootrom
 
 # TODO: Need a clever way of knowing when to repack rocketchip
-$(common)/lib:
+$(common)/lib: $(shell find $(ROCKET_DIR)/. -iname "*.scala" 2> /dev/null)
 	cd $(ROCKET_DIR) && sbt pack
 	mkdir -p $(common)/lib
 	cp $(ROCKET_DIR)/target/pack/lib/* $(common)/lib
+	touch $(common)/lib
 
 $(common_build)/Top.$(CONFIG).fir: $(common)/lib $(common)/bootrom
 	mkdir -p $(@D)
-	cd $(common) && $(SBT) "run zynq Top $(CONFIG) $(CHISEL_ARGS)"
+	cd $(common) && $(SBT) "run zynq Top $(CONFIG_PROJECT) $(CONFIG) $(CHISEL_ARGS)"
 	mv $(common_build)/Top.fir $@
 
 $(common_build)/Top.$(CONFIG).v: $(common_build)/Top.$(CONFIG).fir $(FIRRTL_JAR)
 	$(FIRRTL) -i $< -o $@ -X verilog
 
 src/verilog/Top.$(CONFIG).v: $(common_build)/Top.$(CONFIG).v
-	cp $< $@
 
 rocket: src/verilog/Top.$(CONFIG).v
 
@@ -219,4 +219,4 @@ fetch-riscv-linux-deliver:
 clean:
 	rm -f *.log *.jou *.str
 
-.PHONY: vivado rocket fesvr-zynq fetch-images load-sd ramdisk-open ramdisk-close clean
+.PHONY: vivado pack-rocket rocket fesvr-zynq fetch-images load-sd ramdisk-open ramdisk-close clean

common/src/main/scala/Top.scala

@@ -31,26 +31,14 @@ class Top(implicit val p: Parameters) extends Module
   rocket.io.interrupts map(_ := Bool(false))
 }
 
-/* Would like to disable interrupts in zynq configurations
-class ZynqConfig extends Config(
-  (pname, site, here) => pname match {
-    case NExtInterrupts => 0
-    case _ => throw new CDEMatchError
-  })
-*/
-
-// Do this to avoid looking up the config in a second (in this case, RC) project
-class DefaultFPGAConfig extends Config(new rocketchip.DefaultFPGAConfig)
-class DefaultFPGASmallConfig extends Config(new rocketchip.DefaultFPGASmallConfig)
-
 object Generator extends App {
   val projectName = args(0)
   val topModuleName = args(1)
-  val configClassName = args(2)
+  // arg(2) = rocketchip -> reuse existing rocketchip configurations
+  // arg(2) = zynq -> use new configurations defined here
+  val configProjectName = args(2)
+  val configClassName = args(3)
+  val paramsFromConfig = getParameters(configProjectName, configClassName)
 
-  val config = getConfig(projectName, configClassName)
+  elaborate(s"$projectName.$topModuleName", args.drop(4), paramsFromConfig)
-  val world = config.toInstance
-  val paramsFromConfig = Parameters.root(world)
-
-  elaborate(s"$projectName.$topModuleName", args.drop(3), paramsFromConfig)
 }

zc706/Makefile

@@ -2,6 +2,9 @@ BOARD = zc706
 UBOOT_CONFIG = zc70x
 BOARD_MODEL = xilinx.com:zc706:part0:1.0
 PART = xc7z045ffg900-2
+# CONFIG_PROJECT designates the scala project in which the config is defined
+# This is useful when specifying a configuration already present in rocketchip
+CONFIG_PROJECT ?= rocketchip
 # CONFIG is the target configuration for the rocket-chip generator
 CONFIG ?= DefaultFPGAConfig
 

zedboard/Makefile

@@ -2,6 +2,9 @@ BOARD = zedboard
 UBOOT_CONFIG = zed
 BOARD_MODEL = em.avnet.com:zed:part0:1.0
 PART = xc7z020clg484-1
+# CONFIG_PROJECT designates the scala project in which the config is defined
+# This is useful when specifying a configuration already present in rocketchip
+CONFIG_PROJECT ?= rocketchip
 # CONFIG is the target configuration for the rocket-chip generator
 CONFIG ?= DefaultFPGAConfig
 

zybo/Makefile

@@ -1,6 +1,9 @@
 BOARD = zybo
 UBOOT_CONFIG = $(BOARD)
 PART = xc7z010clg400-1
+# CONFIG_PROJECT designates the scala project in which the config is defined
+# This is useful when specifying a configuration already present in rocketchip
+CONFIG_PROJECT ?= rocketchip
 # CONFIG is the target configuration for the rocket-chip generator
 CONFIG ?= DefaultFPGASmallConfig