hustos
/
fpga-pynq
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

vivado-files

This commit is contained in:
霍振飞 2021-08-19 09:39:11 +00:00 committed by Gitee
parent 53670599a8
commit 9743fcdfc5
2 changed files with 793 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
other-files/base.xdc Normal file
View File

@ -0,0 +1,46 @@
#set_property PACKAGE_PIN H16 [get_ports clk]
#set_property IOSTANDARD LVCMOS33 [get_ports clk]
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports clk]
set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { uart_out }]; #IO_L7P_T1_34 Sch=ja_p[2]
set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { uart_in }]; #IO_L7N_T1_34 Sch=ja_n[2]
set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { uart2_out }]; #IO_L7P_T1_34 Sch=ja_p[2]
set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { uart2_in }]; #IO_L7N_T1_34 Sch=ja_n[2]
##PmodB
set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { pwm_out[0] }]; #IO_L8P_T1_34 Sch=jb_p[1]
set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { pwm_out[1] }]; #IO_L8N_T1_34 Sch=jb_n[1]
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { pwm_out[2] }]; #IO_L1P_T0_34 Sch=jb_p[2]
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { pwm_out[3] }]; #IO_L1N_T0_34 Sch=jb_n[2]
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { clk_out }]; #IO_L18P_T2_34 Sch=jb_p[3]
set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { DIR_enable }]; #IO_L18N_T2_34 Sch=jb_n[3]
set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { DIR_serial }]; #IO_L4P_T0_34 Sch=jb_p[4]
set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { DIR_latch }]; #IO_L4N_T0_34 Sch=jb_n[4]
##LEDs
set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { led_out[0] }]; #IO_L6N_T0_VREF_34 Sch=led[0]
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { led_out[1] }]; #IO_L6P_T0_34 Sch=led[1]
set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led_out[2] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=led[2]
set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led_out[3] }]; #IO_L23P_T3_35 Sch=led[3]
##Buttons
set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L4P_T0_35 Sch=btn[0]
set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4N_T0_35 Sch=btn[1]
set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=btn[2]
set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=btn[3]
## Audio
set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33} [get_ports IIC_1_scl_io]
set_property PULLUP true [get_ports IIC_1_scl_io];
set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports IIC_1_sda_io]
set_property PULLUP true [get_ports IIC_1_sda_io];
set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports audio_clk_10MHz];
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports bclk];
set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports lrclk];
set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports sdata_o];
set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports sdata_i];
set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports {codec_addr[0]}]
set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports {codec_addr[1]}]

747
other-files/rocketchip_wrapper.v Normal file
View File

@ -0,0 +1,747 @@
`timescale 1 ps / 1 ps
`include "clocking.vh"
module rocketchip_wrapper
(
///////////modified///////////
uart_in,
uart_out,
uart2_in,
uart2_out,
pwm_out,
clk_out, //25Mhz
DIR_serial,
DIR_enable,
DIR_latch,
led_out,
btn,
IIC_1_scl_io,
IIC_1_sda_io,
audio_clk_10MHz,
bclk,
codec_addr,
lrclk,
sdata_i,
sdata_o,
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
`ifndef differential_clock
///////////modified///////////
// clk
);
`else
SYSCLK_P,
SYSCLK_N);
`endif
///////////modified///////////
input uart_in;
input uart2_in;
output uart_out;
output uart2_out;
output [3:0]pwm_out;
output clk_out;
output DIR_serial;
output DIR_enable;
output DIR_latch;
assign pwm_out = 4'hf;
output [3:0]led_out;
input [3:0]btn;
inout IIC_1_scl_io;
inout IIC_1_sda_io;
output audio_clk_10MHz;
output bclk;
output [1:0]codec_addr;
output lrclk;
input sdata_i;
output sdata_o;
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
///////////modified///////////
//`ifndef differential_clock
// input clk;
//`else
// input SYSCLK_P;
// input SYSCLK_N;
//`endif
wire FCLK_RESET0_N;
wire [31:0]M_AXI_araddr;
wire [1:0]M_AXI_arburst;
wire [7:0]M_AXI_arlen;
wire M_AXI_arready;
wire [2:0]M_AXI_arsize;
wire M_AXI_arvalid;
wire [31:0]M_AXI_awaddr;
wire [1:0]M_AXI_awburst;
wire [7:0]M_AXI_awlen;
wire [3:0]M_AXI_wstrb;
wire M_AXI_awready;
wire [2:0]M_AXI_awsize;
wire M_AXI_awvalid;
wire M_AXI_bready;
wire M_AXI_bvalid;
wire [31:0]M_AXI_rdata;
wire M_AXI_rlast;
wire M_AXI_rready;
wire M_AXI_rvalid;
wire [31:0]M_AXI_wdata;
wire M_AXI_wlast;
wire M_AXI_wready;
wire M_AXI_wvalid;
wire [11:0] M_AXI_arid, M_AXI_awid; // outputs from ARM core
wire [11:0] M_AXI_bid, M_AXI_rid; // inputs to ARM core
wire S_AXI_arready;
wire S_AXI_arvalid;
wire [31:0] S_AXI_araddr;
wire [5:0] S_AXI_arid;
wire [2:0] S_AXI_arsize;
wire [7:0] S_AXI_arlen;
wire [1:0] S_AXI_arburst;
wire S_AXI_arlock;
wire [3:0] S_AXI_arcache;
wire [2:0] S_AXI_arprot;
wire [3:0] S_AXI_arqos;
//wire [3:0] S_AXI_arregion;
wire S_AXI_awready;
wire S_AXI_awvalid;
wire [31:0] S_AXI_awaddr;
wire [5:0] S_AXI_awid;
wire [2:0] S_AXI_awsize;
wire [7:0] S_AXI_awlen;
wire [1:0] S_AXI_awburst;
wire S_AXI_awlock;
wire [3:0] S_AXI_awcache;
wire [2:0] S_AXI_awprot;
wire [3:0] S_AXI_awqos;
//wire [3:0] S_AXI_awregion;
wire S_AXI_wready;
wire S_AXI_wvalid;
wire [7:0] S_AXI_wstrb;
wire [63:0] S_AXI_wdata;
wire S_AXI_wlast;
wire S_AXI_bready;
wire S_AXI_bvalid;
wire [1:0] S_AXI_bresp;
wire [5:0] S_AXI_bid;
wire S_AXI_rready;
wire S_AXI_rvalid;
wire [1:0] S_AXI_rresp;
wire [5:0] S_AXI_rid;
wire [63:0] S_AXI_rdata;
wire S_AXI_rlast;
wire io_mmio_axi_aw_ready;
wire io_mmio_axi_aw_valid;
wire [3:0] io_mmio_axi_aw_bits_id;
/////////////modified////////////
wire [31:0] io_mmio_axi_aw_bits_addr;
wire [7:0] io_mmio_axi_aw_bits_len;
wire [2:0] io_mmio_axi_aw_bits_size;
wire [1:0] io_mmio_axi_aw_bits_burst;
wire io_mmio_axi_aw_bits_lock;
wire [3:0] io_mmio_axi_aw_bits_cache;
wire [2:0] io_mmio_axi_aw_bits_prot;
wire [3:0] io_mmio_axi_aw_bits_qos;
wire io_mmio_axi_w_ready;
wire io_mmio_axi_w_valid;
wire [63:0] io_mmio_axi_w_bits_data;
wire [7:0] io_mmio_axi_w_bits_strb;
wire io_mmio_axi_w_bits_last;
wire io_mmio_axi_b_ready;
wire io_mmio_axi_b_valid;
wire [3:0] io_mmio_axi_b_bits_id;
wire [1:0] io_mmio_axi_b_bits_resp;
wire io_mmio_axi_ar_ready;
wire io_mmio_axi_ar_valid;
wire [3:0] io_mmio_axi_ar_bits_id;
/////////////modified////////////
wire [31:0] io_mmio_axi_ar_bits_addr;
wire [7:0] io_mmio_axi_ar_bits_len;
wire [2:0] io_mmio_axi_ar_bits_size;
wire [1:0] io_mmio_axi_ar_bits_burst;
wire io_mmio_axi_ar_bits_lock;
wire [3:0] io_mmio_axi_ar_bits_cache;
wire [2:0] io_mmio_axi_ar_bits_prot;
wire [3:0] io_mmio_axi_ar_bits_qos;
wire io_mmio_axi_r_ready;
wire io_mmio_axi_r_valid;
wire [3:0] io_mmio_axi_r_bits_id;
wire [63:0] io_mmio_axi_r_bits_data;
wire [1:0] io_mmio_axi_r_bits_resp;
wire io_mmio_axi_r_bits_last;
wire IIC_1_scl_i;
wire IIC_1_scl_io;
wire IIC_1_scl_o;
wire IIC_1_scl_t;
wire IIC_1_sda_i;
wire IIC_1_sda_io;
wire IIC_1_sda_o;
wire IIC_1_sda_t;
wire [1:0] rocket_interrupts;
wire [7:0] gpio_out;
wire [63:0]GPIO_0;
assign led_out = GPIO_0[3:0];
// assign rocket_interrupts = btn[1:0];
IOBUF IIC_1_scl_iobuf
(.I(IIC_1_scl_o),
.IO(IIC_1_scl_io),
.O(IIC_1_scl_i),
.T(IIC_1_scl_t));
IOBUF IIC_1_sda_iobuf
(.I(IIC_1_sda_o),
.IO(IIC_1_sda_io),
.O(IIC_1_sda_i),
.T(IIC_1_sda_t));
wire reset, reset_cpu;
wire host_clk;
wire gclk_i, gclk_fbout, host_clk_i, mmcm_locked;
system system_i
(
/////////////modified////////////
.uart_in(uart_in),
.uart_out(uart_out),
.uart2_in(uart2_in),
.uart2_out(uart2_out),
.gpio_out(gpio_out),
.IIC_1_scl_i(IIC_1_scl_i),
.IIC_1_scl_o(IIC_1_scl_o),
.IIC_1_scl_t(IIC_1_scl_t),
.IIC_1_sda_i(IIC_1_sda_i),
.IIC_1_sda_o(IIC_1_sda_o),
.IIC_1_sda_t(IIC_1_sda_t),
.audio_clk_10MHz(audio_clk_10MHz),
.bclk(bclk),
.codec_addr(codec_addr),
.lrclk(lrclk),
.sdata_i(sdata_i),
.sdata_o(sdata_o),
.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
// master AXI interface (zynq = master, fpga = slave)
.M_AXI_araddr(M_AXI_araddr),
.M_AXI_arburst(M_AXI_arburst), // burst type
.M_AXI_arcache(),
.M_AXI_arid(M_AXI_arid),
.M_AXI_arlen(M_AXI_arlen), // burst length (#transfers)
.M_AXI_arlock(),
.M_AXI_arprot(),
.M_AXI_arqos(),
.M_AXI_arready(M_AXI_arready),
.M_AXI_arregion(),
.M_AXI_arsize(M_AXI_arsize), // burst size (bits/transfer)
.M_AXI_arvalid(M_AXI_arvalid),
//
.M_AXI_awaddr(M_AXI_awaddr),
.M_AXI_awburst(M_AXI_awburst),
.M_AXI_awcache(),
.M_AXI_awid(M_AXI_awid),
.M_AXI_awlen(M_AXI_awlen),
.M_AXI_awlock(),
.M_AXI_awprot(),
.M_AXI_awqos(),
.M_AXI_awready(M_AXI_awready),
.M_AXI_awregion(),
.M_AXI_awsize(M_AXI_awsize),
.M_AXI_awvalid(M_AXI_awvalid),
//
.M_AXI_bid(M_AXI_bid),
.M_AXI_bready(M_AXI_bready),
.M_AXI_bresp(2'b00),
.M_AXI_bvalid(M_AXI_bvalid),
//
.M_AXI_rdata(M_AXI_rdata),
.M_AXI_rid(M_AXI_rid),
.M_AXI_rlast(M_AXI_rlast),
.M_AXI_rready(M_AXI_rready),
.M_AXI_rresp(),
.M_AXI_rvalid(M_AXI_rvalid),
//
.M_AXI_wdata(M_AXI_wdata),
.M_AXI_wlast(M_AXI_wlast),
.M_AXI_wready(M_AXI_wready),
.M_AXI_wstrb(M_AXI_wstrb),
.M_AXI_wvalid(M_AXI_wvalid),
// slave AXI interface (fpga = master, zynq = slave)
// connected directly to DDR controller to handle test chip mem
.S_AXI_araddr(S_AXI_araddr),
.S_AXI_arburst(S_AXI_arburst),
.S_AXI_arcache(S_AXI_arcache),
.S_AXI_arid(S_AXI_arid),
.S_AXI_arlen(S_AXI_arlen),
.S_AXI_arlock(S_AXI_arlock),
.S_AXI_arprot(S_AXI_arprot),
.S_AXI_arqos(S_AXI_arqos),
.S_AXI_arready(S_AXI_arready),
.S_AXI_arregion(4'b0),
.S_AXI_arsize(S_AXI_arsize),
.S_AXI_arvalid(S_AXI_arvalid),
//
.S_AXI_awaddr(S_AXI_awaddr),
.S_AXI_awburst(S_AXI_awburst),
.S_AXI_awcache(S_AXI_awcache),
.S_AXI_awid(S_AXI_awid),
.S_AXI_awlen(S_AXI_awlen),
.S_AXI_awlock(S_AXI_awlock),
.S_AXI_awprot(S_AXI_awprot),
.S_AXI_awqos(S_AXI_awqos),
.S_AXI_awready(S_AXI_awready),
.S_AXI_awregion(4'b0),
.S_AXI_awsize(S_AXI_awsize),
.S_AXI_awvalid(S_AXI_awvalid),
//
.S_AXI_bid(S_AXI_bid),
.S_AXI_bready(S_AXI_bready),
.S_AXI_bresp(S_AXI_bresp),
.S_AXI_bvalid(S_AXI_bvalid),
//
.S_AXI_rid(S_AXI_rid),
.S_AXI_rdata(S_AXI_rdata),
.S_AXI_rlast(S_AXI_rlast),
.S_AXI_rready(S_AXI_rready),
.S_AXI_rresp(S_AXI_rresp),
.S_AXI_rvalid(S_AXI_rvalid),
//
.S_AXI_wdata(S_AXI_wdata),
.S_AXI_wlast(S_AXI_wlast),
.S_AXI_wready(S_AXI_wready),
.S_AXI_wstrb(S_AXI_wstrb),
.S_AXI_wvalid(S_AXI_wvalid),
///////////modified///////////
.FCLK_CLK0(host_clk),
// .ext_clk_in(host_clk),
///////////modified///////////
.MMIO_S_AXI_araddr(io_mmio_axi_ar_bits_addr),
.MMIO_S_AXI_arburst(io_mmio_axi_ar_bits_burst),
.MMIO_S_AXI_arcache(io_mmio_axi_ar_bits_cache),
.MMIO_S_AXI_arid(io_mmio_axi_ar_bits_id),
.MMIO_S_AXI_arlen(io_mmio_axi_ar_bits_len),
.MMIO_S_AXI_arlock(io_mmio_axi_ar_bits_lock),
.MMIO_S_AXI_arprot(io_mmio_axi_ar_bits_prot),
.MMIO_S_AXI_arqos(io_mmio_axi_ar_bits_qos),
.MMIO_S_AXI_arready(io_mmio_axi_ar_ready),
// .MMIO_S_AXI_arregion(4'b0),
.MMIO_S_AXI_arsize(io_mmio_axi_ar_bits_size),
.MMIO_S_AXI_arvalid(io_mmio_axi_ar_valid),
.MMIO_S_AXI_awaddr(io_mmio_axi_aw_bits_addr),
.MMIO_S_AXI_awburst(io_mmio_axi_aw_bits_burst),
.MMIO_S_AXI_awcache(io_mmio_axi_aw_bits_cache),
.MMIO_S_AXI_awid(io_mmio_axi_aw_bits_id),
.MMIO_S_AXI_awlen(io_mmio_axi_aw_bits_len),
.MMIO_S_AXI_awlock(io_mmio_axi_aw_bits_lock),
.MMIO_S_AXI_awprot(io_mmio_axi_aw_bits_prot),
.MMIO_S_AXI_awqos(io_mmio_axi_aw_bits_qos),
.MMIO_S_AXI_awready(io_mmio_axi_aw_ready),
// .MMIO_S_AXI_awregion(4'b0),
.MMIO_S_AXI_awsize(io_mmio_axi_aw_bits_size),
.MMIO_S_AXI_awvalid(io_mmio_axi_aw_valid),
.MMIO_S_AXI_bid(io_mmio_axi_b_bits_id),
.MMIO_S_AXI_bready(io_mmio_axi_b_ready),
.MMIO_S_AXI_bresp(io_mmio_axi_b_bits_resp),
.MMIO_S_AXI_bvalid(io_mmio_axi_b_valid),
.MMIO_S_AXI_rid(io_mmio_axi_r_bits_id),
.MMIO_S_AXI_rdata(io_mmio_axi_r_bits_data),
.MMIO_S_AXI_rlast(io_mmio_axi_r_bits_last),
.MMIO_S_AXI_rready(io_mmio_axi_r_ready),
.MMIO_S_AXI_rresp(io_mmio_axi_r_bits_resp),
.MMIO_S_AXI_rvalid(io_mmio_axi_r_valid),
.MMIO_S_AXI_wdata(io_mmio_axi_w_bits_data),
.MMIO_S_AXI_wlast(io_mmio_axi_w_bits_last),
.MMIO_S_AXI_wready(io_mmio_axi_w_ready),
.MMIO_S_AXI_wstrb(io_mmio_axi_w_bits_strb),
.MMIO_S_AXI_wvalid(io_mmio_axi_w_valid),
.GPIO_0(GPIO_0),
.interrupts(rocket_interrupts)
);
///////////modified///////////
// assign reset = !FCLK_RESET0_N || !mmcm_locked;
assign reset = !FCLK_RESET0_N;
wire [31:0] mem_araddr;
wire [31:0] mem_awaddr;
///////////modified///////////
// Memory given to Rocket is the upper 256 MB of the 512 MB DRAM
// assign S_AXI_araddr = {4'd1, mem_araddr[27:0]};
// assign S_AXI_awaddr = {4'd1, mem_awaddr[27:0]};
assign S_AXI_araddr = mem_araddr - 32'h70000000;
assign S_AXI_awaddr = mem_awaddr - 32'h70000000;
Top top(
.clock(host_clk),
.reset(reset),
.io_ps_axi_slave_aw_ready (M_AXI_awready),
.io_ps_axi_slave_aw_valid (M_AXI_awvalid),
.io_ps_axi_slave_aw_bits_addr (M_AXI_awaddr),
.io_ps_axi_slave_aw_bits_len (M_AXI_awlen),
.io_ps_axi_slave_aw_bits_size (M_AXI_awsize),
.io_ps_axi_slave_aw_bits_burst (M_AXI_awburst),
.io_ps_axi_slave_aw_bits_id (M_AXI_awid),
.io_ps_axi_slave_aw_bits_lock (1'b0),
.io_ps_axi_slave_aw_bits_cache (4'b0),
.io_ps_axi_slave_aw_bits_prot (3'b0),
.io_ps_axi_slave_aw_bits_qos (4'b0),
.io_ps_axi_slave_ar_ready (M_AXI_arready),
.io_ps_axi_slave_ar_valid (M_AXI_arvalid),
.io_ps_axi_slave_ar_bits_addr (M_AXI_araddr),
.io_ps_axi_slave_ar_bits_len (M_AXI_arlen),
.io_ps_axi_slave_ar_bits_size (M_AXI_arsize),
.io_ps_axi_slave_ar_bits_burst (M_AXI_arburst),
.io_ps_axi_slave_ar_bits_id (M_AXI_arid),
.io_ps_axi_slave_ar_bits_lock (1'b0),
.io_ps_axi_slave_ar_bits_cache (4'b0),
.io_ps_axi_slave_ar_bits_prot (3'b0),
.io_ps_axi_slave_ar_bits_qos (4'b0),
.io_ps_axi_slave_w_valid (M_AXI_wvalid),
.io_ps_axi_slave_w_ready (M_AXI_wready),
.io_ps_axi_slave_w_bits_data (M_AXI_wdata),
.io_ps_axi_slave_w_bits_strb (M_AXI_wstrb),
.io_ps_axi_slave_w_bits_last (M_AXI_wlast),
.io_ps_axi_slave_r_valid (M_AXI_rvalid),
.io_ps_axi_slave_r_ready (M_AXI_rready),
.io_ps_axi_slave_r_bits_id (M_AXI_rid),
.io_ps_axi_slave_r_bits_resp (M_AXI_rresp),
.io_ps_axi_slave_r_bits_data (M_AXI_rdata),
.io_ps_axi_slave_r_bits_last (M_AXI_rlast),
.io_ps_axi_slave_b_valid (M_AXI_bvalid),
.io_ps_axi_slave_b_ready (M_AXI_bready),
.io_ps_axi_slave_b_bits_id (M_AXI_bid),
.io_ps_axi_slave_b_bits_resp (M_AXI_bresp),
.io_mem_axi_ar_valid (S_AXI_arvalid),
.io_mem_axi_ar_ready (S_AXI_arready),
.io_mem_axi_ar_bits_addr (mem_araddr),
.io_mem_axi_ar_bits_id (S_AXI_arid),
.io_mem_axi_ar_bits_size (S_AXI_arsize),
.io_mem_axi_ar_bits_len (S_AXI_arlen),
.io_mem_axi_ar_bits_burst (S_AXI_arburst),
.io_mem_axi_ar_bits_cache (S_AXI_arcache),
.io_mem_axi_ar_bits_lock (S_AXI_arlock),
.io_mem_axi_ar_bits_prot (S_AXI_arprot),
.io_mem_axi_ar_bits_qos (S_AXI_arqos),
.io_mem_axi_aw_valid (S_AXI_awvalid),
.io_mem_axi_aw_ready (S_AXI_awready),
.io_mem_axi_aw_bits_addr (mem_awaddr),
.io_mem_axi_aw_bits_id (S_AXI_awid),
.io_mem_axi_aw_bits_size (S_AXI_awsize),
.io_mem_axi_aw_bits_len (S_AXI_awlen),
.io_mem_axi_aw_bits_burst (S_AXI_awburst),
.io_mem_axi_aw_bits_cache (S_AXI_awcache),
.io_mem_axi_aw_bits_lock (S_AXI_awlock),
.io_mem_axi_aw_bits_prot (S_AXI_awprot),
.io_mem_axi_aw_bits_qos (S_AXI_awqos),
.io_mem_axi_w_valid (S_AXI_wvalid),
.io_mem_axi_w_ready (S_AXI_wready),
.io_mem_axi_w_bits_strb (S_AXI_wstrb),
.io_mem_axi_w_bits_data (S_AXI_wdata),
.io_mem_axi_w_bits_last (S_AXI_wlast),
.io_mem_axi_b_valid (S_AXI_bvalid),
.io_mem_axi_b_ready (S_AXI_bready),
.io_mem_axi_b_bits_resp (S_AXI_bresp),
.io_mem_axi_b_bits_id (S_AXI_bid),
.io_mem_axi_r_valid (S_AXI_rvalid),
.io_mem_axi_r_ready (S_AXI_rready),
.io_mem_axi_r_bits_resp (S_AXI_rresp),
.io_mem_axi_r_bits_id (S_AXI_rid),
.io_mem_axi_r_bits_data (S_AXI_rdata),
.io_mem_axi_r_bits_last (S_AXI_rlast),
///////////modified///////////
.io_mmio_axi_aw_ready(io_mmio_axi_aw_ready),
.io_mmio_axi_aw_valid(io_mmio_axi_aw_valid),
.io_mmio_axi_aw_bits_id(io_mmio_axi_aw_bits_id),
.io_mmio_axi_aw_bits_addr(io_mmio_axi_aw_bits_addr),
.io_mmio_axi_aw_bits_len(io_mmio_axi_aw_bits_len),
.io_mmio_axi_aw_bits_size(io_mmio_axi_aw_bits_size),
.io_mmio_axi_aw_bits_burst(io_mmio_axi_aw_bits_burst),
.io_mmio_axi_aw_bits_lock(io_mmio_axi_aw_bits_lock),
.io_mmio_axi_aw_bits_cache(io_mmio_axi_aw_bits_cache),
.io_mmio_axi_aw_bits_prot(io_mmio_axi_aw_bits_prot),
.io_mmio_axi_aw_bits_qos(io_mmio_axi_aw_bits_qos),
.io_mmio_axi_w_ready(io_mmio_axi_w_ready),
.io_mmio_axi_w_valid(io_mmio_axi_w_valid),
.io_mmio_axi_w_bits_data(io_mmio_axi_w_bits_data),
.io_mmio_axi_w_bits_strb(io_mmio_axi_w_bits_strb),
.io_mmio_axi_w_bits_last(io_mmio_axi_w_bits_last),
.io_mmio_axi_b_ready(io_mmio_axi_b_ready),
.io_mmio_axi_b_valid(io_mmio_axi_b_valid),
.io_mmio_axi_b_bits_id(io_mmio_axi_b_bits_id),
.io_mmio_axi_b_bits_resp(io_mmio_axi_b_bits_resp),
.io_mmio_axi_ar_ready(io_mmio_axi_ar_ready),
.io_mmio_axi_ar_valid(io_mmio_axi_ar_valid),
.io_mmio_axi_ar_bits_id(io_mmio_axi_ar_bits_id),
.io_mmio_axi_ar_bits_addr(io_mmio_axi_ar_bits_addr),
.io_mmio_axi_ar_bits_len(io_mmio_axi_ar_bits_len),
.io_mmio_axi_ar_bits_size(io_mmio_axi_ar_bits_size),
.io_mmio_axi_ar_bits_burst(io_mmio_axi_ar_bits_burst),
.io_mmio_axi_ar_bits_lock(io_mmio_axi_ar_bits_lock),
.io_mmio_axi_ar_bits_cache(io_mmio_axi_ar_bits_cache),
.io_mmio_axi_ar_bits_prot(io_mmio_axi_ar_bits_prot),
.io_mmio_axi_ar_bits_qos(io_mmio_axi_ar_bits_qos),
.io_mmio_axi_r_ready(io_mmio_axi_r_ready),
.io_mmio_axi_r_valid(io_mmio_axi_r_valid),
.io_mmio_axi_r_bits_id(io_mmio_axi_r_bits_id),
.io_mmio_axi_r_bits_data(io_mmio_axi_r_bits_data),
.io_mmio_axi_r_bits_resp(io_mmio_axi_r_bits_resp),
.io_mmio_axi_r_bits_last(io_mmio_axi_r_bits_last),
.io_interrupt_in(rocket_interrupts)
);
///////////modified///////////
//`ifndef differential_clock
// IBUFG ibufg_gclk (.I(clk), .O(gclk_i));
//`else
// IBUFDS #(.DIFF_TERM("TRUE"), .IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) clk_ibufds (.O(gclk_i), .I(SYSCLK_P), .IB(SYSCLK_N));
//`endif
// BUFG bufg_host_clk (.I(host_clk_i), .O(host_clk));
// MMCME2_BASE #(
// .BANDWIDTH("OPTIMIZED"),
// .CLKFBOUT_MULT_F(`RC_CLK_MULT),
// .CLKFBOUT_PHASE(0.0),
// .CLKIN1_PERIOD(`ZYNQ_CLK_PERIOD),
// .CLKOUT1_DIVIDE(1),
// .CLKOUT2_DIVIDE(1),
// .CLKOUT3_DIVIDE(1),
// .CLKOUT4_DIVIDE(1),
// .CLKOUT5_DIVIDE(1),
// .CLKOUT6_DIVIDE(1),
// .CLKOUT0_DIVIDE_F(`RC_CLK_DIVIDE),
// .CLKOUT0_DUTY_CYCLE(0.5),
// .CLKOUT1_DUTY_CYCLE(0.5),
// .CLKOUT2_DUTY_CYCLE(0.5),
// .CLKOUT3_DUTY_CYCLE(0.5),
// .CLKOUT4_DUTY_CYCLE(0.5),
// .CLKOUT5_DUTY_CYCLE(0.5),
// .CLKOUT6_DUTY_CYCLE(0.5),
// .CLKOUT0_PHASE(0.0),
// .CLKOUT1_PHASE(0.0),
// .CLKOUT2_PHASE(0.0),
// .CLKOUT3_PHASE(0.0),
// .CLKOUT4_PHASE(0.0),
// .CLKOUT5_PHASE(0.0),
// .CLKOUT6_PHASE(0.0),
// .CLKOUT4_CASCADE("FALSE"),
// .DIVCLK_DIVIDE(1),
// .REF_JITTER1(0.0),
// .STARTUP_WAIT("FALSE")
// ) MMCME2_BASE_inst (
// .CLKOUT0(host_clk_i),
// .CLKOUT0B(),
// .CLKOUT1(),
// .CLKOUT1B(),
// .CLKOUT2(),
// .CLKOUT2B(),
// .CLKOUT3(),
// .CLKOUT3B(),
// .CLKOUT4(),
// .CLKOUT5(),
// .CLKOUT6(),
// .CLKFBOUT(gclk_fbout),
// .CLKFBOUTB(),
// .LOCKED(mmcm_locked),
// .CLKIN1(gclk_i),
// .PWRDWN(1'b0),
// .RST(1'b0),
// .CLKFBIN(gclk_fbout));
Car_Driver_Int car_driver(
.clk_in(host_clk),
.CtrlSig(gpio_out),
.clk_out(clk_out),
.DIR_serial(DIR_serial),
.DIR_enable(DIR_enable),
.DIR_latch(DIR_latch)
);
endmodule
module Car_Driver_Int (
input clk_in,
input [7:0] CtrlSig,
output reg clk_out,
output reg DIR_serial,
output reg DIR_enable,
output reg DIR_latch
);
parameter ST0 = 0, ST1 = 1, ST2 = 2, ST3 = 3, ST4 = 4, ST5 = 5, ST6 = 6, ST7 = 7, ST8 = 8;
reg [3: 0] p_state = ST8;
reg [7:0] buff = 0;
initial begin
clk_out = 1'b0;
end
always @ (posedge clk_in) begin //2鍒嗛
clk_out <= ~clk_out;
end
always @ (negedge clk_out)
case (p_state)
ST0:
begin
buff <= CtrlSig;
p_state <= ST1;
DIR_serial <= CtrlSig[0];
DIR_enable <= 1;
DIR_latch <= 0;
end
ST1:
begin
p_state <= ST2;
DIR_serial <= CtrlSig[1];
DIR_enable <= 1;
DIR_latch <= 0;
end
ST2:
begin
p_state <= ST3;
DIR_serial <= CtrlSig[2];
DIR_enable <= 1;
DIR_latch <= 0;
end
ST3:
begin
p_state <= ST4;
DIR_serial <= CtrlSig[3];
DIR_enable <= 1;
DIR_latch <= 0;
end
ST4:
begin
p_state <= ST5;
DIR_serial <= CtrlSig[4];
DIR_enable <= 1;
DIR_latch <= 0;
end
ST5:
begin
p_state <= ST6;
DIR_serial <= CtrlSig[5];
DIR_enable <= 1;
DIR_latch <= 0;
end
ST6:
begin
p_state <= ST7;
DIR_serial <= CtrlSig[6];
DIR_enable <= 1;
DIR_latch <= 0;
end
ST7:
begin
p_state <= ST8;
DIR_serial <= CtrlSig[7];
DIR_enable <= 1;
DIR_latch <= 0;
end
ST8:
begin
p_state = !(CtrlSig ^ buff) ? ST8 : ST0;
DIR_serial <= CtrlSig[7];
DIR_enable <= 0;
DIR_latch <= 1;
end
default:
begin
p_state <= ST8;
end
endcase
endmodule