move TestDriver.v into testchipip
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@ -1,91 +0,0 @@
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// See LICENSE for license details.
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`ifndef RESET_DELAY
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`define RESET_DELAY 777.7
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`endif
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module TestDriver;
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reg clock = 1'b0;
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reg reset = 1'b1;
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always #(`CLOCK_PERIOD/2.0) clock = ~clock;
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initial #(`RESET_DELAY) reset = 0;
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// Read input arguments and initialize
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reg verbose = 1'b0;
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wire printf_cond = verbose && !reset;
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reg [63:0] max_cycles = 0;
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reg [63:0] trace_count = 0;
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reg [1023:0] vcdplusfile = 0;
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reg [1023:0] vcdfile = 0;
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initial
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begin
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$value$plusargs("max-cycles=%d", max_cycles);
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verbose = $test$plusargs("verbose");
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`ifdef DEBUG
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if ($value$plusargs("vcdplusfile=%s", vcdplusfile))
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begin
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$vcdplusfile(vcdplusfile);
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$vcdpluson(0);
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$vcdplusmemon(0);
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end
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if ($value$plusargs("vcdfile=%s", vcdfile))
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begin
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$dumpfile(vcdfile);
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$dumpvars(0, testHarness);
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$dumpon;
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end
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`define VCDPLUSCLOSE $vcdplusclose; $dumpoff;
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`else
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`define VCDPLUSCLOSE
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`endif
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end
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reg [255:0] reason = "";
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reg failure = 1'b0;
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wire success;
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integer stderr = 32'h80000002;
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always @(posedge clock)
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begin
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`ifdef GATE_LEVEL
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if (verbose)
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begin
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$fdisplay(stderr, "C: %10d", trace_count);
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end
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`endif
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trace_count = trace_count + 1;
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if (!reset)
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begin
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if (max_cycles > 0 && trace_count > max_cycles)
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begin
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reason = " (timeout)";
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failure = 1'b1;
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end
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if (failure)
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begin
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$fdisplay(stderr, "*** FAILED ***%s after %d simulation cycles", reason, trace_count);
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`VCDPLUSCLOSE
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$fatal;
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end
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if (success)
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begin
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if (verbose)
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$fdisplay(stderr, "Completed after %d simulation cycles", trace_count);
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`VCDPLUSCLOSE
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$finish;
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end
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end
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end
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TestHarness testHarness(
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.clock (clock),
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.reset (reset),
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.io_success (success)
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);
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endmodule
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@ -12,7 +12,7 @@ include ../common/Makefrag
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sim_vsrcs = \
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src/verilog/$(TOP_MODULE).$(CONFIG).v \
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$(common)/vsrc/TestDriver.v \
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$(base_dir)/testchipip/vsrc/TestDriver.v \
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$(base_dir)/testchipip/vsrc/SimSerial.v
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sim_csrcs = \
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@ -1 +1 @@
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Subproject commit fdd6612edc4ee63e1afb2b69cc429b5b80ce4474
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Subproject commit 1302c62a32c89e54c9967f3007845827e4c6f7d0
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