From 4f13b7fd39afa6103e646be1bb10ae5938dd68ab Mon Sep 17 00:00:00 2001 From: Scott Beamer Date: Wed, 6 Jan 2016 09:37:05 -0800 Subject: [PATCH] port zc706 block design to 2015.4 --- zc706/src/tcl/zc706_bd.tcl | 401 ++++++++++++++++++++++++++----------- 1 file changed, 287 insertions(+), 114 deletions(-) diff --git a/zc706/src/tcl/zc706_bd.tcl b/zc706/src/tcl/zc706_bd.tcl index 48807e1..2a49aa7 100644 --- a/zc706/src/tcl/zc706_bd.tcl +++ b/zc706/src/tcl/zc706_bd.tcl @@ -10,7 +10,7 @@ ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2015.2 +set scripts_vivado_version 2015.4 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { @@ -147,135 +147,281 @@ proc create_root_design { parentCell } { set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] set M_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI ] - set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.FREQ_HZ {50000000} CONFIG.PROTOCOL {AXI4} ] $M_AXI + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {50000000} \ +CONFIG.PROTOCOL {AXI4} \ + ] $M_AXI set S_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI ] - set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.ARUSER_WIDTH {0} CONFIG.AWUSER_WIDTH {0} CONFIG.BUSER_WIDTH {0} CONFIG.CLK_DOMAIN {} CONFIG.DATA_WIDTH {64} CONFIG.FREQ_HZ {50000000} CONFIG.ID_WIDTH {6} CONFIG.MAX_BURST_LENGTH {16} CONFIG.NUM_READ_OUTSTANDING {1} CONFIG.NUM_WRITE_OUTSTANDING {1} CONFIG.PHASE {0.000} CONFIG.PROTOCOL {AXI4} CONFIG.READ_WRITE_MODE {READ_WRITE} CONFIG.RUSER_WIDTH {0} CONFIG.SUPPORTS_NARROW_BURST {1} CONFIG.WUSER_WIDTH {0} ] $S_AXI + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.ARUSER_WIDTH {0} \ +CONFIG.AWUSER_WIDTH {0} \ +CONFIG.BUSER_WIDTH {0} \ +CONFIG.DATA_WIDTH {64} \ +CONFIG.FREQ_HZ {50000000} \ +CONFIG.HAS_BRESP {1} \ +CONFIG.HAS_BURST {1} \ +CONFIG.HAS_CACHE {1} \ +CONFIG.HAS_LOCK {1} \ +CONFIG.HAS_PROT {1} \ +CONFIG.HAS_QOS {1} \ +CONFIG.HAS_REGION {1} \ +CONFIG.HAS_RRESP {1} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.ID_WIDTH {6} \ +CONFIG.MAX_BURST_LENGTH {16} \ +CONFIG.NUM_READ_OUTSTANDING {1} \ +CONFIG.NUM_WRITE_OUTSTANDING {1} \ +CONFIG.PHASE {0.000} \ +CONFIG.PROTOCOL {AXI4} \ +CONFIG.READ_WRITE_MODE {READ_WRITE} \ +CONFIG.RUSER_WIDTH {0} \ +CONFIG.SUPPORTS_NARROW_BURST {1} \ +CONFIG.WUSER_WIDTH {0} \ + ] $S_AXI # Create ports set FCLK_RESET0_N [ create_bd_port -dir O -type rst FCLK_RESET0_N ] set ext_clk_in [ create_bd_port -dir I -type clk ext_clk_in ] - set_property -dict [ list CONFIG.ASSOCIATED_BUSIF {S_AXI:M_AXI} CONFIG.FREQ_HZ {50000000} ] $ext_clk_in + set_property -dict [ list \ +CONFIG.ASSOCIATED_BUSIF {S_AXI:M_AXI} \ +CONFIG.FREQ_HZ {50000000} \ + ] $ext_clk_in # Create instance: axi_interconnect_0, and set properties set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] - set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_interconnect_0 + set_property -dict [ list \ +CONFIG.NUM_MI {1} \ + ] $axi_interconnect_0 # Create instance: axi_interconnect_1, and set properties set axi_interconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_1 ] - set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_interconnect_1 + set_property -dict [ list \ +CONFIG.NUM_MI {1} \ + ] $axi_interconnect_1 # Create instance: proc_sys_reset_0, and set properties set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] - set_property -dict [ list CONFIG.C_AUX_RESET_HIGH {0} ] $proc_sys_reset_0 + set_property -dict [ list \ +CONFIG.C_AUX_RESET_HIGH {0} \ + ] $proc_sys_reset_0 # Create instance: processing_system7_0, and set properties set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] - set_property -dict [ list CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {25.000000} \ -CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ -CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {50.000000} \ -CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {667.000000} CONFIG.PCW_CLK0_FREQ {100000000} \ -CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {1} CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \ -CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ -CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ -CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {100 Mbps} CONFIG.PCW_EN_ENET0 {1} \ -CONFIG.PCW_EN_QSPI {1} CONFIG.PCW_EN_SDIO0 {1} \ -CONFIG.PCW_EN_UART1 {1} CONFIG.PCW_EN_USB0 {1} \ -CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {0} \ -CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_0_PULLUP {enabled} CONFIG.PCW_MIO_0_SLEW {slow} \ -CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_10_PULLUP {enabled} \ -CONFIG.PCW_MIO_10_SLEW {slow} CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_11_PULLUP {enabled} CONFIG.PCW_MIO_11_SLEW {slow} \ -CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_12_PULLUP {enabled} \ -CONFIG.PCW_MIO_12_SLEW {slow} CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_13_PULLUP {enabled} CONFIG.PCW_MIO_13_SLEW {slow} \ -CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_14_PULLUP {enabled} \ -CONFIG.PCW_MIO_14_SLEW {slow} CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_15_PULLUP {enabled} CONFIG.PCW_MIO_15_SLEW {slow} \ -CONFIG.PCW_MIO_16_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_16_PULLUP {disabled} \ -CONFIG.PCW_MIO_16_SLEW {slow} CONFIG.PCW_MIO_17_IOTYPE {HSTL 1.8V} \ -CONFIG.PCW_MIO_17_PULLUP {disabled} CONFIG.PCW_MIO_17_SLEW {slow} \ -CONFIG.PCW_MIO_18_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_18_PULLUP {disabled} \ -CONFIG.PCW_MIO_18_SLEW {slow} CONFIG.PCW_MIO_19_IOTYPE {HSTL 1.8V} \ -CONFIG.PCW_MIO_19_PULLUP {disabled} CONFIG.PCW_MIO_19_SLEW {slow} \ -CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_1_PULLUP {enabled} \ -CONFIG.PCW_MIO_1_SLEW {slow} CONFIG.PCW_MIO_20_IOTYPE {HSTL 1.8V} \ -CONFIG.PCW_MIO_20_PULLUP {disabled} CONFIG.PCW_MIO_20_SLEW {slow} \ -CONFIG.PCW_MIO_21_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_21_PULLUP {disabled} \ -CONFIG.PCW_MIO_21_SLEW {slow} CONFIG.PCW_MIO_22_IOTYPE {HSTL 1.8V} \ -CONFIG.PCW_MIO_22_PULLUP {disabled} CONFIG.PCW_MIO_22_SLEW {slow} \ -CONFIG.PCW_MIO_23_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_23_PULLUP {disabled} \ -CONFIG.PCW_MIO_23_SLEW {slow} CONFIG.PCW_MIO_24_IOTYPE {HSTL 1.8V} \ -CONFIG.PCW_MIO_24_PULLUP {disabled} CONFIG.PCW_MIO_24_SLEW {slow} \ -CONFIG.PCW_MIO_25_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_25_PULLUP {disabled} \ -CONFIG.PCW_MIO_25_SLEW {slow} CONFIG.PCW_MIO_26_IOTYPE {HSTL 1.8V} \ -CONFIG.PCW_MIO_26_PULLUP {disabled} CONFIG.PCW_MIO_26_SLEW {slow} \ -CONFIG.PCW_MIO_27_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_27_PULLUP {disabled} \ -CONFIG.PCW_MIO_27_SLEW {slow} CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_28_PULLUP {disabled} CONFIG.PCW_MIO_28_SLEW {slow} \ -CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_29_PULLUP {disabled} \ -CONFIG.PCW_MIO_29_SLEW {slow} CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_2_SLEW {slow} CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_30_PULLUP {disabled} CONFIG.PCW_MIO_30_SLEW {slow} \ -CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_31_PULLUP {disabled} \ -CONFIG.PCW_MIO_31_SLEW {slow} CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_32_PULLUP {disabled} CONFIG.PCW_MIO_32_SLEW {slow} \ -CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_33_PULLUP {disabled} \ -CONFIG.PCW_MIO_33_SLEW {slow} CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_34_PULLUP {disabled} CONFIG.PCW_MIO_34_SLEW {slow} \ -CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_35_PULLUP {disabled} \ -CONFIG.PCW_MIO_35_SLEW {slow} CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_36_PULLUP {disabled} CONFIG.PCW_MIO_36_SLEW {slow} \ -CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_37_PULLUP {disabled} \ -CONFIG.PCW_MIO_37_SLEW {slow} CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_38_PULLUP {disabled} CONFIG.PCW_MIO_38_SLEW {slow} \ -CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_39_PULLUP {disabled} \ -CONFIG.PCW_MIO_39_SLEW {slow} CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_3_SLEW {slow} CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_40_PULLUP {disabled} CONFIG.PCW_MIO_40_SLEW {slow} \ -CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_41_PULLUP {disabled} \ -CONFIG.PCW_MIO_41_SLEW {slow} CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_42_PULLUP {disabled} CONFIG.PCW_MIO_42_SLEW {slow} \ -CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_43_PULLUP {disabled} \ -CONFIG.PCW_MIO_43_SLEW {slow} CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_44_PULLUP {disabled} CONFIG.PCW_MIO_44_SLEW {slow} \ -CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_45_PULLUP {disabled} \ -CONFIG.PCW_MIO_45_SLEW {slow} CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_48_PULLUP {disabled} CONFIG.PCW_MIO_48_SLEW {slow} \ -CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_49_PULLUP {disabled} \ -CONFIG.PCW_MIO_49_SLEW {slow} CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_4_SLEW {slow} CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_52_PULLUP {disabled} CONFIG.PCW_MIO_52_SLEW {slow} \ -CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_53_PULLUP {disabled} \ -CONFIG.PCW_MIO_53_SLEW {slow} CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_5_SLEW {slow} CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_6_SLEW {slow} CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_8_SLEW {slow} CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_9_PULLUP {enabled} CONFIG.PCW_MIO_9_SLEW {slow} \ -CONFIG.PCW_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#SD 0#SD 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#unassigned#unassigned#UART 1#UART 1#unassigned#unassigned#Enet 0#Enet 0} CONFIG.PCW_MIO_TREE_SIGNALS {qspi1_ss_b#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#unassigned#qspi_fbclk#qspi1_sclk#qspi1_io[0]#qspi1_io[1]#qspi1_io[2]#qspi1_io[3]#cd#wp#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#unassigned#unassigned#tx#rx#unassigned#unassigned#mdc#mdio} \ -CONFIG.PCW_M_AXI_GP0_FREQMHZ {50} CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {1} \ -CONFIG.PCW_PERIPHERAL_BOARD_PRESET {part0} CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} \ -CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \ -CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} CONFIG.PCW_QSPI_GRP_IO1_ENABLE {1} \ -CONFIG.PCW_QSPI_GRP_IO1_IO {MIO 0 9 .. 13} CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \ -CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \ -CONFIG.PCW_SD0_GRP_CD_IO {MIO 14} CONFIG.PCW_SD0_GRP_WP_ENABLE {1} \ -CONFIG.PCW_SD0_GRP_WP_IO {MIO 15} CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ -CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \ -CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} CONFIG.PCW_S_AXI_HP0_FREQMHZ {50} \ -CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0} CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \ -CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {50} \ -CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.521} CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.636} \ -CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.54} CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.621} \ -CONFIG.PCW_UIPARAM_DDR_CWL {5.000000} CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {2048 MBits} \ -CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.226} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.278} \ -CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.184} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.309} \ -CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333313} CONFIG.PCW_UIPARAM_DDR_PARTNO {Custom} \ -CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \ -CONFIG.PCW_UIPARAM_DDR_T_FAW {25} CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {36.0} \ -CONFIG.PCW_UIPARAM_DDR_T_RC {49.5} CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {1} \ -CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \ -CONFIG.PCW_USE_S_AXI_HP0 {1} CONFIG.preset {ZC706} \ + set_property -dict [ list \ +CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {25.000000} \ +CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ +CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ +CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \ +CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {50.000000} \ +CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {667.000000} \ +CONFIG.PCW_CLK0_FREQ {100000000} \ +CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {1} \ +CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \ +CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ +CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ +CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ +CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {100 Mbps} \ +CONFIG.PCW_EN_ENET0 {1} \ +CONFIG.PCW_EN_QSPI {1} \ +CONFIG.PCW_EN_SDIO0 {1} \ +CONFIG.PCW_EN_UART1 {1} \ +CONFIG.PCW_EN_USB0 {1} \ +CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ +CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {0} \ +CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_0_PULLUP {enabled} \ +CONFIG.PCW_MIO_0_SLEW {slow} \ +CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_10_PULLUP {enabled} \ +CONFIG.PCW_MIO_10_SLEW {slow} \ +CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_11_PULLUP {enabled} \ +CONFIG.PCW_MIO_11_SLEW {slow} \ +CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_12_PULLUP {enabled} \ +CONFIG.PCW_MIO_12_SLEW {slow} \ +CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_13_PULLUP {enabled} \ +CONFIG.PCW_MIO_13_SLEW {slow} \ +CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_14_PULLUP {enabled} \ +CONFIG.PCW_MIO_14_SLEW {slow} \ +CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_15_PULLUP {enabled} \ +CONFIG.PCW_MIO_15_SLEW {slow} \ +CONFIG.PCW_MIO_16_IOTYPE {HSTL 1.8V} \ +CONFIG.PCW_MIO_16_PULLUP {disabled} \ +CONFIG.PCW_MIO_16_SLEW {slow} \ +CONFIG.PCW_MIO_17_IOTYPE {HSTL 1.8V} \ +CONFIG.PCW_MIO_17_PULLUP {disabled} \ +CONFIG.PCW_MIO_17_SLEW {slow} \ +CONFIG.PCW_MIO_18_IOTYPE {HSTL 1.8V} \ +CONFIG.PCW_MIO_18_PULLUP {disabled} \ +CONFIG.PCW_MIO_18_SLEW {slow} \ +CONFIG.PCW_MIO_19_IOTYPE {HSTL 1.8V} \ +CONFIG.PCW_MIO_19_PULLUP {disabled} \ +CONFIG.PCW_MIO_19_SLEW {slow} \ +CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_1_PULLUP {enabled} \ +CONFIG.PCW_MIO_1_SLEW {slow} \ +CONFIG.PCW_MIO_20_IOTYPE {HSTL 1.8V} \ +CONFIG.PCW_MIO_20_PULLUP {disabled} \ +CONFIG.PCW_MIO_20_SLEW {slow} \ +CONFIG.PCW_MIO_21_IOTYPE {HSTL 1.8V} \ +CONFIG.PCW_MIO_21_PULLUP {disabled} \ +CONFIG.PCW_MIO_21_SLEW {slow} \ +CONFIG.PCW_MIO_22_IOTYPE {HSTL 1.8V} \ +CONFIG.PCW_MIO_22_PULLUP {disabled} \ +CONFIG.PCW_MIO_22_SLEW {slow} \ +CONFIG.PCW_MIO_23_IOTYPE {HSTL 1.8V} \ +CONFIG.PCW_MIO_23_PULLUP {disabled} \ +CONFIG.PCW_MIO_23_SLEW {slow} \ +CONFIG.PCW_MIO_24_IOTYPE {HSTL 1.8V} \ +CONFIG.PCW_MIO_24_PULLUP {disabled} \ +CONFIG.PCW_MIO_24_SLEW {slow} \ +CONFIG.PCW_MIO_25_IOTYPE {HSTL 1.8V} \ +CONFIG.PCW_MIO_25_PULLUP {disabled} \ +CONFIG.PCW_MIO_25_SLEW {slow} \ +CONFIG.PCW_MIO_26_IOTYPE {HSTL 1.8V} \ +CONFIG.PCW_MIO_26_PULLUP {disabled} \ +CONFIG.PCW_MIO_26_SLEW {slow} \ +CONFIG.PCW_MIO_27_IOTYPE {HSTL 1.8V} \ +CONFIG.PCW_MIO_27_PULLUP {disabled} \ +CONFIG.PCW_MIO_27_SLEW {slow} \ +CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_28_PULLUP {disabled} \ +CONFIG.PCW_MIO_28_SLEW {slow} \ +CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_29_PULLUP {disabled} \ +CONFIG.PCW_MIO_29_SLEW {slow} \ +CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_2_SLEW {slow} \ +CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_30_PULLUP {disabled} \ +CONFIG.PCW_MIO_30_SLEW {slow} \ +CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_31_PULLUP {disabled} \ +CONFIG.PCW_MIO_31_SLEW {slow} \ +CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_32_PULLUP {disabled} \ +CONFIG.PCW_MIO_32_SLEW {slow} \ +CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_33_PULLUP {disabled} \ +CONFIG.PCW_MIO_33_SLEW {slow} \ +CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_34_PULLUP {disabled} \ +CONFIG.PCW_MIO_34_SLEW {slow} \ +CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_35_PULLUP {disabled} \ +CONFIG.PCW_MIO_35_SLEW {slow} \ +CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_36_PULLUP {disabled} \ +CONFIG.PCW_MIO_36_SLEW {slow} \ +CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_37_PULLUP {disabled} \ +CONFIG.PCW_MIO_37_SLEW {slow} \ +CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_38_PULLUP {disabled} \ +CONFIG.PCW_MIO_38_SLEW {slow} \ +CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_39_PULLUP {disabled} \ +CONFIG.PCW_MIO_39_SLEW {slow} \ +CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_3_SLEW {slow} \ +CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_40_PULLUP {disabled} \ +CONFIG.PCW_MIO_40_SLEW {slow} \ +CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_41_PULLUP {disabled} \ +CONFIG.PCW_MIO_41_SLEW {slow} \ +CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_42_PULLUP {disabled} \ +CONFIG.PCW_MIO_42_SLEW {slow} \ +CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_43_PULLUP {disabled} \ +CONFIG.PCW_MIO_43_SLEW {slow} \ +CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_44_PULLUP {disabled} \ +CONFIG.PCW_MIO_44_SLEW {slow} \ +CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_45_PULLUP {disabled} \ +CONFIG.PCW_MIO_45_SLEW {slow} \ +CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_48_PULLUP {disabled} \ +CONFIG.PCW_MIO_48_SLEW {slow} \ +CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_49_PULLUP {disabled} \ +CONFIG.PCW_MIO_49_SLEW {slow} \ +CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_4_SLEW {slow} \ +CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_52_PULLUP {disabled} \ +CONFIG.PCW_MIO_52_SLEW {slow} \ +CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_53_PULLUP {disabled} \ +CONFIG.PCW_MIO_53_SLEW {slow} \ +CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_5_SLEW {slow} \ +CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_6_SLEW {slow} \ +CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_8_SLEW {slow} \ +CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_9_PULLUP {enabled} \ +CONFIG.PCW_MIO_9_SLEW {slow} \ +CONFIG.PCW_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#SD 0#SD 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#unassigned#unassigned#UART 1#UART 1#unassigned#unassigned#Enet 0#Enet 0} \ +CONFIG.PCW_MIO_TREE_SIGNALS {qspi1_ss_b#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#unassigned#qspi_fbclk#qspi1_sclk#qspi1_io[0]#qspi1_io[1]#qspi1_io[2]#qspi1_io[3]#cd#wp#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#unassigned#unassigned#tx#rx#unassigned#unassigned#mdc#mdio} \ +CONFIG.PCW_M_AXI_GP0_FREQMHZ {50} \ +CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {1} \ +CONFIG.PCW_PERIPHERAL_BOARD_PRESET {part0} \ +CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} \ +CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ +CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \ +CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \ +CONFIG.PCW_QSPI_GRP_IO1_ENABLE {1} \ +CONFIG.PCW_QSPI_GRP_IO1_IO {MIO 0 9 .. 13} \ +CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \ +CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \ +CONFIG.PCW_SD0_GRP_CD_IO {MIO 14} \ +CONFIG.PCW_SD0_GRP_WP_ENABLE {1} \ +CONFIG.PCW_SD0_GRP_WP_IO {MIO 15} \ +CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \ +CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ +CONFIG.PCW_S_AXI_HP0_FREQMHZ {50} \ +CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \ +CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.521} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.636} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.54} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.621} \ +CONFIG.PCW_UIPARAM_DDR_CWL {5.000000} \ +CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {2048 MBits} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.226} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.278} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.184} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.309} \ +CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333313} \ +CONFIG.PCW_UIPARAM_DDR_PARTNO {Custom} \ +CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ +CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \ +CONFIG.PCW_UIPARAM_DDR_T_FAW {25} \ +CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {36.0} \ +CONFIG.PCW_UIPARAM_DDR_T_RC {49.5} \ +CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {1} \ +CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \ +CONFIG.PCW_USE_S_AXI_HP0 {1} \ +CONFIG.preset {ZC706} \ ] $processing_system7_0 # Create interface connections @@ -295,7 +441,34 @@ CONFIG.PCW_USE_S_AXI_HP0 {1} CONFIG.preset {ZC706} \ # Create address segments create_bd_addr_seg -range 0x1000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI/Reg] SEG_system_Reg create_bd_addr_seg -range 0x20000000 -offset 0x0 [get_bd_addr_spaces S_AXI] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM - + + # Perform GUI Layout + regenerate_bd_layout -layout_string { + guistr: "# # String gsaved with Nlview 6.5.5 2015-06-26 bk=1.3371 VDI=38 GEI=35 GUI=JA:1.8 +# -string -flagsOSRD +preplace port DDR -pg 1 -y 100 -defaultsOSRD +preplace port FCLK_RESET0_N -pg 1 -y 360 -defaultsOSRD +preplace port S_AXI -pg 1 -y 70 -defaultsOSRD +preplace port M_AXI -pg 1 -y 240 -defaultsOSRD +preplace port FIXED_IO -pg 1 -y 120 -defaultsOSRD +preplace port ext_clk_in -pg 1 -y 250 -defaultsOSRD +preplace inst proc_sys_reset_0 -pg 1 -lvl 1 -y 350 -defaultsOSRD +preplace inst axi_interconnect_0 -pg 1 -lvl 4 -y 240 -defaultsOSRD +preplace inst axi_interconnect_1 -pg 1 -lvl 2 -y 130 -defaultsOSRD +preplace inst processing_system7_0 -pg 1 -lvl 3 -y 140 -defaultsOSRD +preplace netloc S_AXI_1 1 0 2 NJ 70 NJ +preplace netloc processing_system7_0_DDR 1 3 2 NJ 100 NJ +preplace netloc processing_system7_0_M_AXI_GP0 1 3 1 1110 +preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 5 30 260 NJ 260 NJ 260 1110 360 NJ +preplace netloc proc_sys_reset_0_interconnect_aresetn 1 1 3 370 250 NJ 250 1120 +preplace netloc processing_system7_0_FIXED_IO 1 3 2 NJ 120 NJ +preplace netloc axi_interconnect_0_M00_AXI 1 4 1 NJ +preplace netloc proc_sys_reset_0_peripheral_aresetn 1 1 3 390 270 NJ 270 1140 +preplace netloc axi_interconnect_1_M00_AXI 1 2 1 N +preplace netloc ext_clk_in_1 1 0 4 20 170 380 10 670 30 1130 +levelinfo -pg 1 0 200 530 890 1280 1440 -top 0 -bot 440 +", +} # Restore current instance current_bd_instance $oldCurInst