fix deprecation warnings
This commit is contained in:
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2aea76181a
commit
4994d21937
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@ -25,29 +25,29 @@ class IntegrationTestDriver(implicit p: Parameters) extends NastiModule()(p) {
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val testLen = 0x40
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val readAddr = Reg(UInt(4.W))
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val (cmd_read :: cmd_write :: Nil) = Enum(Bits(), 2)
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val (cmd_read :: cmd_write :: Nil) = Enum(2)
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val (s_idle :: s_write_addr :: s_write_data :: s_write_resp ::
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s_read_addr :: s_read_data :: s_done :: Nil) = Enum(Bits(), 7)
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s_read_addr :: s_read_data :: s_done :: Nil) = Enum(7)
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val state = Reg(init = s_idle)
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val testData = Vec(Seq.tabulate(testLen)(i => UInt(i * 3)))
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val testData = Vec(Seq.tabulate(testLen)(i => (i * 3).U))
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val idx = Reg(UInt(32.W))
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val writeData = MuxCase(UInt(0), Seq(
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(idx === UInt(0)) -> cmd_write,
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(idx === UInt(1)) -> UInt(startAddr),
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(idx === UInt(3)) -> UInt(testLen - 1),
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(idx >= UInt(5) && idx < UInt(5 + testLen)) -> testData(idx - UInt(5)),
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(idx === UInt(5 + testLen)) -> cmd_read,
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(idx === UInt(6 + testLen)) -> UInt(startAddr),
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(idx === UInt(8 + testLen)) -> UInt(testLen - 1)))
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val writeData = MuxCase(0.U, Seq(
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(idx === 0.U) -> cmd_write,
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(idx === 1.U) -> startAddr.U,
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(idx === 3.U) -> (testLen - 1).U,
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(idx >= 5.U && idx < (5 + testLen).U) -> testData(idx - 5.U),
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(idx === (5 + testLen).U) -> cmd_read,
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(idx === (6 + testLen).U) -> startAddr.U,
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(idx === (8 + testLen).U) -> (testLen - 1).U))
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val lastWriteIdx = 9 + testLen
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when (state === s_idle) {
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idx := UInt(0)
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readAddr := UInt(0x0)
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idx := 0.U
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readAddr := 0x0.U
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state := s_write_addr
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}
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@ -60,11 +60,11 @@ class IntegrationTestDriver(implicit p: Parameters) extends NastiModule()(p) {
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}
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when (io.nasti.b.fire()) {
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when (idx === UInt(lastWriteIdx)) {
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idx := UInt(0)
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when (idx === lastWriteIdx.U) {
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idx := 0.U
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state := s_read_addr
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} .otherwise {
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idx := idx + UInt(1)
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idx := idx + 1.U
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state := s_write_addr
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}
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}
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@ -75,17 +75,17 @@ class IntegrationTestDriver(implicit p: Parameters) extends NastiModule()(p) {
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when (io.nasti.r.fire()) {
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switch (readAddr) {
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is (UInt(0x0)) {
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when (idx === UInt(testLen - 1)) {
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is (0x0.U) {
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when (idx === (testLen - 1).U) {
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state := s_read_addr
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readAddr := UInt(0x4)
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readAddr := 0x4.U
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} .otherwise {
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idx := idx + UInt(1)
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idx := idx + 1.U
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state := s_read_addr
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}
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}
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is (UInt(0x4)) { readAddr := UInt(0xC); state := s_read_addr }
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is (UInt(0xC)) { state := s_done }
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is (0x4.U) { readAddr := 0xC.U; state := s_read_addr }
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is (0xC.U) { state := s_done }
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}
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}
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@ -93,26 +93,26 @@ class IntegrationTestDriver(implicit p: Parameters) extends NastiModule()(p) {
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io.nasti.aw.valid := (state === s_write_addr)
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io.nasti.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = UInt(0x43C00008L),
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size = UInt(2))
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id = 0.U,
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addr = 0x43C00008L.U,
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size = 2.U)
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io.nasti.w.valid := (state === s_write_data)
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io.nasti.w.bits := NastiWriteDataChannel(data = writeData)
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io.nasti.ar.valid := (state === s_read_addr)
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io.nasti.ar.bits := NastiReadAddressChannel(
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id = UInt(0),
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addr = UInt(0x43C00000L) | readAddr,
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size = UInt(2))
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id = 0.U,
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addr = 0x43C00000L.U | readAddr,
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size = 2.U)
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io.nasti.b.ready := (state === s_write_resp)
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io.nasti.r.ready := (state === s_read_data)
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val expectedData = MuxLookup(readAddr, UInt(0), Seq(
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UInt(0xC) -> UInt(p(SerialFIFODepth)),
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UInt(0x4) -> UInt(0),
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UInt(0x0) -> testData(idx)))
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val expectedData = MuxLookup(readAddr, 0.U, Seq(
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0xC.U -> p(SerialFIFODepth).U,
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0x4.U -> 0.U,
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0x0.U -> testData(idx)))
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assert(!io.nasti.b.valid || io.nasti.b.bits.resp === RESP_OKAY,
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"Integration test write error")
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@ -125,7 +125,7 @@ class IntegrationTestReset(implicit p: Parameters) extends Module {
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val nasti = new NastiIO
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})
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val (s_idle :: s_write_addr :: s_write_data :: s_done :: Nil) = Enum(Bits(), 4)
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val (s_idle :: s_write_addr :: s_write_data :: s_done :: Nil) = Enum(4)
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val state = Reg(init = s_idle)
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when (state === s_idle) { state := s_write_addr }
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@ -134,16 +134,16 @@ class IntegrationTestReset(implicit p: Parameters) extends Module {
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io.nasti.aw.valid := state === s_write_addr
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io.nasti.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = UInt(0x43C00010L),
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size = UInt(2))
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id = 0.U,
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addr = 0x43C00010L.U,
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size = 2.U)
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io.nasti.w.valid := state === s_write_data
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io.nasti.w.bits := NastiWriteDataChannel(data = UInt(0))
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io.nasti.w.bits := NastiWriteDataChannel(data = 0.U)
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io.nasti.b.ready := (state === s_done)
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io.nasti.ar.valid := Bool(false)
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io.nasti.r.ready := Bool(false)
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io.nasti.ar.valid := false.B
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io.nasti.r.ready := false.B
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}
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class IntegrationTestSerial(implicit p: Parameters) extends SerialDriver(p(SerialInterfaceWidth)) {
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@ -26,9 +26,9 @@ class TestHarness(implicit val p: Parameters) extends Module {
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class DummyTile(implicit p: Parameters) extends Tile()(p) {
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def tieOff(cached: ClientTileLinkIO) {
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cached.acquire.valid := Bool(false)
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cached.grant.ready := Bool(false)
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cached.finish.valid := Bool(false)
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cached.acquire.valid := false.B
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cached.grant.ready := false.B
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cached.finish.valid := false.B
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val prb = Queue(cached.probe)
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cached.release.valid := prb.valid
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@ -37,8 +37,8 @@ class DummyTile(implicit p: Parameters) extends Tile()(p) {
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}
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def tieOff(uncached: ClientUncachedTileLinkIO) {
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uncached.acquire.valid := Bool(false)
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uncached.grant.ready := Bool(false)
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uncached.acquire.valid := false.B
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uncached.grant.ready := false.B
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}
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io.cached.foreach(tieOff(_))
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@ -70,11 +70,11 @@ class ResetController(implicit p: Parameters) extends NastiModule()(p) {
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val sys_reset = Output(Bool())
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})
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val reg_reset = Reg(init = Bool(true))
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val reg_reset = Reg(init = true.B)
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val readId = Reg(UInt(nastiXIdBits.W))
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val r_addr :: r_data :: Nil = Enum(Bits(), 2)
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val r_addr :: r_data :: Nil = Enum(2)
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val r_state = Reg(init = r_addr)
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io.nasti.ar.ready := r_state === r_addr
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@ -94,12 +94,12 @@ class ResetController(implicit p: Parameters) extends NastiModule()(p) {
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val writeId = Reg(UInt(nastiXIdBits.W))
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val w_addr :: w_data :: w_resp :: Nil = Enum(Bits(), 3)
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val w_addr :: w_data :: w_resp :: Nil = Enum(3)
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val w_state = Reg(init = w_addr)
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val timer = Reg(init = UInt(p(ResetCycles) - 1))
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val timer = Reg(init = (p(ResetCycles) - 1).U)
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// Make sure reset period lasts for a certain number of cycles
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when (timer =/= UInt(0)) { timer := timer - UInt(1) }
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when (timer =/= 0.U) { timer := timer - 1.U }
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when (io.nasti.aw.fire()) {
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writeId := io.nasti.aw.bits.id
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@ -107,7 +107,7 @@ class ResetController(implicit p: Parameters) extends NastiModule()(p) {
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}
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when (io.nasti.w.fire()) {
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timer := UInt(p(ResetCycles) - 1)
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timer := (p(ResetCycles) - 1).U
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reg_reset := io.nasti.w.bits.data(0)
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w_state := w_resp
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}
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@ -118,7 +118,7 @@ class ResetController(implicit p: Parameters) extends NastiModule()(p) {
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io.nasti.aw.ready := w_state === w_addr
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io.nasti.w.ready := w_state === w_data
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io.nasti.b.valid := w_state === w_resp && timer === UInt(0)
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io.nasti.b.valid := w_state === w_resp && timer === 0.U
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io.nasti.b.bits := NastiWriteResponseChannel(id = writeId)
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io.sys_reset := reg_reset
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@ -138,9 +138,9 @@ class NastiFIFO(implicit p: Parameters) extends NastiModule()(p) {
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val outq = Module(new Queue(UInt(w.W), depth))
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val inq = Module(new Queue(UInt(w.W), depth))
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val writing = Reg(init = Bool(false))
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val reading = Reg(init = Bool(false))
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val responding = Reg(init = Bool(false))
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val writing = Reg(init = false.B)
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val reading = Reg(init = false.B)
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val responding = Reg(init = false.B)
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val len = Reg(UInt(nastiXLenBits.W))
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val bid = Reg(UInt(nastiXIdBits.W))
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val rid = Reg(UInt(nastiXIdBits.W))
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@ -156,8 +156,8 @@ class NastiFIFO(implicit p: Parameters) extends NastiModule()(p) {
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val raddr = Reg(araddr)
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val waddr = Reg(awaddr)
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inq.io.enq.valid := io.nasti.w.valid && writing && (waddr === UInt(2))
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io.nasti.w.ready := (inq.io.enq.ready || waddr =/= UInt(2)) && writing
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inq.io.enq.valid := io.nasti.w.valid && writing && (waddr === 2.U)
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io.nasti.w.ready := (inq.io.enq.ready || waddr =/= 2.U) && writing
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inq.io.enq.bits := io.nasti.w.bits.data
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/**
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@ -167,15 +167,15 @@ class NastiFIFO(implicit p: Parameters) extends NastiModule()(p) {
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* 0x08 - in FIFO data
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* 0x0C - in FIFO space available (words)
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*/
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io.nasti.r.valid := reading && (raddr =/= UInt(0) || outq.io.deq.valid)
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outq.io.deq.ready := reading && raddr === UInt(0) && io.nasti.r.ready
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io.nasti.r.valid := reading && (raddr =/= 0.U || outq.io.deq.valid)
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outq.io.deq.ready := reading && raddr === 0.U && io.nasti.r.ready
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io.nasti.r.bits := NastiReadDataChannel(
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id = rid,
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data = MuxLookup(raddr, UInt(0), Seq(
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UInt(0) -> outq.io.deq.bits,
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UInt(1) -> outq.io.count,
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UInt(3) -> (UInt(depth) - inq.io.count))),
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last = len === UInt(0))
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data = MuxLookup(raddr, 0.U, Seq(
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0.U -> outq.io.deq.bits,
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1.U -> outq.io.count,
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3.U -> (depth.U - inq.io.count))),
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last = len === 0.U)
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io.nasti.aw.ready := !writing && !responding
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io.nasti.ar.ready := !reading
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@ -183,33 +183,33 @@ class NastiFIFO(implicit p: Parameters) extends NastiModule()(p) {
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io.nasti.b.bits := NastiWriteResponseChannel(
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id = bid,
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// writing to anything other that the in FIFO is an error
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resp = Mux(waddr === UInt(2), RESP_OKAY, RESP_SLVERR))
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resp = Mux(waddr === 2.U, RESP_OKAY, RESP_SLVERR))
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when (io.nasti.aw.fire()) {
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writing := Bool(true)
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writing := true.B
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waddr := awaddr
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bid := io.nasti.aw.bits.id
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}
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when (io.nasti.w.fire() && io.nasti.w.bits.last) {
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writing := Bool(false)
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responding := Bool(true)
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writing := false.B
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responding := true.B
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}
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when (io.nasti.b.fire()) { responding := Bool(false) }
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when (io.nasti.b.fire()) { responding := false.B }
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when (io.nasti.ar.fire()) {
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len := io.nasti.ar.bits.len
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rid := io.nasti.ar.bits.id
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raddr := araddr
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reading := Bool(true)
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reading := true.B
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}
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when (io.nasti.r.fire()) {
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len := len - UInt(1)
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when (len === UInt(0)) { reading := Bool(false) }
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len := len - 1.U
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when (len === 0.U) { reading := false.B }
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}
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def addressOK(chan: NastiAddressChannel): Bool =
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(chan.len === UInt(0) || chan.burst === BURST_FIXED) &&
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chan.size === UInt(log2Up(w/8)) &&
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chan.addr(log2Up(nastiWStrobeBits)-1, 0) === UInt(0)
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(chan.len === 0.U || chan.burst === BURST_FIXED) &&
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chan.size === log2Up(w/8).U &&
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chan.addr(log2Up(nastiWStrobeBits)-1, 0) === 0.U
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def dataOK(chan: NastiWriteDataChannel): Bool =
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chan.strb(w/8-1, 0).andR
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@ -1 +1 @@
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Subproject commit 69b66e4b1d893672d3c6f2fa3797394f391c096c
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Subproject commit 4b6fe076cfab3c685fd6201559221cbad858c77e
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