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fpga-pynq
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fix deprecation warnings

This commit is contained in:
Howard Mao 2017-02-08 13:37:19 -08:00
parent 2aea76181a
commit 4994d21937
4 changed files with 75 additions and 75 deletions
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78
common/src/main/scala/SerialDriver.scala
View File

@ -25,29 +25,29 @@ class IntegrationTestDriver(implicit p: Parameters) extends NastiModule()(p) {
val testLen = 0x40 val testLen = 0x40
val readAddr = Reg(UInt(4.W)) val readAddr = Reg(UInt(4.W))
val (cmd_read :: cmd_write :: Nil) = Enum(Bits(), 2) val (cmd_read :: cmd_write :: Nil) = Enum(2)
val (s_idle :: s_write_addr :: s_write_data :: s_write_resp :: val (s_idle :: s_write_addr :: s_write_data :: s_write_resp ::
s_read_addr :: s_read_data :: s_done :: Nil) = Enum(Bits(), 7) s_read_addr :: s_read_data :: s_done :: Nil) = Enum(7)
val state = Reg(init = s_idle) val state = Reg(init = s_idle)
val testData = Vec(Seq.tabulate(testLen)(i => UInt(i * 3))) val testData = Vec(Seq.tabulate(testLen)(i => (i * 3).U))
val idx = Reg(UInt(32.W)) val idx = Reg(UInt(32.W))
val writeData = MuxCase(UInt(0), Seq( val writeData = MuxCase(0.U, Seq(
(idx === UInt(0)) -> cmd_write, (idx === 0.U) -> cmd_write,
(idx === UInt(1)) -> UInt(startAddr), (idx === 1.U) -> startAddr.U,
(idx === UInt(3)) -> UInt(testLen - 1), (idx === 3.U) -> (testLen - 1).U,
(idx >= UInt(5) && idx < UInt(5 + testLen)) -> testData(idx - UInt(5)), (idx >= 5.U && idx < (5 + testLen).U) -> testData(idx - 5.U),
(idx === UInt(5 + testLen)) -> cmd_read, (idx === (5 + testLen).U) -> cmd_read,
(idx === UInt(6 + testLen)) -> UInt(startAddr), (idx === (6 + testLen).U) -> startAddr.U,
(idx === UInt(8 + testLen)) -> UInt(testLen - 1))) (idx === (8 + testLen).U) -> (testLen - 1).U))
val lastWriteIdx = 9 + testLen val lastWriteIdx = 9 + testLen
when (state === s_idle) { when (state === s_idle) {
idx := UInt(0) idx := 0.U
readAddr := UInt(0x0) readAddr := 0x0.U
state := s_write_addr state := s_write_addr
} }
@ -60,11 +60,11 @@ class IntegrationTestDriver(implicit p: Parameters) extends NastiModule()(p) {
} }
when (io.nasti.b.fire()) { when (io.nasti.b.fire()) {
when (idx === UInt(lastWriteIdx)) { when (idx === lastWriteIdx.U) {
idx := UInt(0) idx := 0.U
state := s_read_addr state := s_read_addr
} .otherwise { } .otherwise {
idx := idx + UInt(1) idx := idx + 1.U
state := s_write_addr state := s_write_addr
} }
} }
@ -75,17 +75,17 @@ class IntegrationTestDriver(implicit p: Parameters) extends NastiModule()(p) {
when (io.nasti.r.fire()) { when (io.nasti.r.fire()) {
switch (readAddr) { switch (readAddr) {
is (UInt(0x0)) { is (0x0.U) {
when (idx === UInt(testLen - 1)) { when (idx === (testLen - 1).U) {
state := s_read_addr state := s_read_addr
readAddr := UInt(0x4) readAddr := 0x4.U
} .otherwise { } .otherwise {
idx := idx + UInt(1) idx := idx + 1.U
state := s_read_addr state := s_read_addr
} }
} }
is (UInt(0x4)) { readAddr := UInt(0xC); state := s_read_addr } is (0x4.U) { readAddr := 0xC.U; state := s_read_addr }
is (UInt(0xC)) { state := s_done } is (0xC.U) { state := s_done }
} }
} }
@ -93,26 +93,26 @@ class IntegrationTestDriver(implicit p: Parameters) extends NastiModule()(p) {
io.nasti.aw.valid := (state === s_write_addr) io.nasti.aw.valid := (state === s_write_addr)
io.nasti.aw.bits := NastiWriteAddressChannel( io.nasti.aw.bits := NastiWriteAddressChannel(
id = UInt(0), id = 0.U,
addr = UInt(0x43C00008L), addr = 0x43C00008L.U,
size = UInt(2)) size = 2.U)
io.nasti.w.valid := (state === s_write_data) io.nasti.w.valid := (state === s_write_data)
io.nasti.w.bits := NastiWriteDataChannel(data = writeData) io.nasti.w.bits := NastiWriteDataChannel(data = writeData)
io.nasti.ar.valid := (state === s_read_addr) io.nasti.ar.valid := (state === s_read_addr)
io.nasti.ar.bits := NastiReadAddressChannel( io.nasti.ar.bits := NastiReadAddressChannel(
id = UInt(0), id = 0.U,
addr = UInt(0x43C00000L) | readAddr, addr = 0x43C00000L.U | readAddr,
size = UInt(2)) size = 2.U)
io.nasti.b.ready := (state === s_write_resp) io.nasti.b.ready := (state === s_write_resp)
io.nasti.r.ready := (state === s_read_data) io.nasti.r.ready := (state === s_read_data)
val expectedData = MuxLookup(readAddr, UInt(0), Seq( val expectedData = MuxLookup(readAddr, 0.U, Seq(
UInt(0xC) -> UInt(p(SerialFIFODepth)), 0xC.U -> p(SerialFIFODepth).U,
UInt(0x4) -> UInt(0), 0x4.U -> 0.U,
UInt(0x0) -> testData(idx))) 0x0.U -> testData(idx)))
assert(!io.nasti.b.valid || io.nasti.b.bits.resp === RESP_OKAY, assert(!io.nasti.b.valid || io.nasti.b.bits.resp === RESP_OKAY,
"Integration test write error") "Integration test write error")
@ -125,7 +125,7 @@ class IntegrationTestReset(implicit p: Parameters) extends Module {
val nasti = new NastiIO val nasti = new NastiIO
}) })
val (s_idle :: s_write_addr :: s_write_data :: s_done :: Nil) = Enum(Bits(), 4) val (s_idle :: s_write_addr :: s_write_data :: s_done :: Nil) = Enum(4)
val state = Reg(init = s_idle) val state = Reg(init = s_idle)
when (state === s_idle) { state := s_write_addr } when (state === s_idle) { state := s_write_addr }
@ -134,16 +134,16 @@ class IntegrationTestReset(implicit p: Parameters) extends Module {
io.nasti.aw.valid := state === s_write_addr io.nasti.aw.valid := state === s_write_addr
io.nasti.aw.bits := NastiWriteAddressChannel( io.nasti.aw.bits := NastiWriteAddressChannel(
id = UInt(0), id = 0.U,
addr = UInt(0x43C00010L), addr = 0x43C00010L.U,
size = UInt(2)) size = 2.U)
io.nasti.w.valid := state === s_write_data io.nasti.w.valid := state === s_write_data
io.nasti.w.bits := NastiWriteDataChannel(data = UInt(0)) io.nasti.w.bits := NastiWriteDataChannel(data = 0.U)
io.nasti.b.ready := (state === s_done) io.nasti.b.ready := (state === s_done)
io.nasti.ar.valid := Bool(false) io.nasti.ar.valid := false.B
io.nasti.r.ready := Bool(false) io.nasti.r.ready := false.B
} }
class IntegrationTestSerial(implicit p: Parameters) extends SerialDriver(p(SerialInterfaceWidth)) { class IntegrationTestSerial(implicit p: Parameters) extends SerialDriver(p(SerialInterfaceWidth)) {

10
common/src/main/scala/TestHarness.scala
View File

@ -26,9 +26,9 @@ class TestHarness(implicit val p: Parameters) extends Module {
class DummyTile(implicit p: Parameters) extends Tile()(p) { class DummyTile(implicit p: Parameters) extends Tile()(p) {
def tieOff(cached: ClientTileLinkIO) { def tieOff(cached: ClientTileLinkIO) {
cached.acquire.valid := Bool(false) cached.acquire.valid := false.B
cached.grant.ready := Bool(false) cached.grant.ready := false.B
cached.finish.valid := Bool(false) cached.finish.valid := false.B
val prb = Queue(cached.probe) val prb = Queue(cached.probe)
cached.release.valid := prb.valid cached.release.valid := prb.valid
@ -37,8 +37,8 @@ class DummyTile(implicit p: Parameters) extends Tile()(p) {
} }
def tieOff(uncached: ClientUncachedTileLinkIO) { def tieOff(uncached: ClientUncachedTileLinkIO) {
uncached.acquire.valid := Bool(false) uncached.acquire.valid := false.B
uncached.grant.ready := Bool(false) uncached.grant.ready := false.B
} }
io.cached.foreach(tieOff(_)) io.cached.foreach(tieOff(_))

60
common/src/main/scala/Top.scala
View File

@ -70,11 +70,11 @@ class ResetController(implicit p: Parameters) extends NastiModule()(p) {
val sys_reset = Output(Bool()) val sys_reset = Output(Bool())
}) })
val reg_reset = Reg(init = Bool(true)) val reg_reset = Reg(init = true.B)
val readId = Reg(UInt(nastiXIdBits.W)) val readId = Reg(UInt(nastiXIdBits.W))
val r_addr :: r_data :: Nil = Enum(Bits(), 2) val r_addr :: r_data :: Nil = Enum(2)
val r_state = Reg(init = r_addr) val r_state = Reg(init = r_addr)
io.nasti.ar.ready := r_state === r_addr io.nasti.ar.ready := r_state === r_addr
@ -94,12 +94,12 @@ class ResetController(implicit p: Parameters) extends NastiModule()(p) {
val writeId = Reg(UInt(nastiXIdBits.W)) val writeId = Reg(UInt(nastiXIdBits.W))
val w_addr :: w_data :: w_resp :: Nil = Enum(Bits(), 3) val w_addr :: w_data :: w_resp :: Nil = Enum(3)
val w_state = Reg(init = w_addr) val w_state = Reg(init = w_addr)
val timer = Reg(init = UInt(p(ResetCycles) - 1)) val timer = Reg(init = (p(ResetCycles) - 1).U)
// Make sure reset period lasts for a certain number of cycles // Make sure reset period lasts for a certain number of cycles
when (timer =/= UInt(0)) { timer := timer - UInt(1) } when (timer =/= 0.U) { timer := timer - 1.U }
when (io.nasti.aw.fire()) { when (io.nasti.aw.fire()) {
writeId := io.nasti.aw.bits.id writeId := io.nasti.aw.bits.id
@ -107,7 +107,7 @@ class ResetController(implicit p: Parameters) extends NastiModule()(p) {
} }
when (io.nasti.w.fire()) { when (io.nasti.w.fire()) {
timer := UInt(p(ResetCycles) - 1) timer := (p(ResetCycles) - 1).U
reg_reset := io.nasti.w.bits.data(0) reg_reset := io.nasti.w.bits.data(0)
w_state := w_resp w_state := w_resp
} }
@ -118,7 +118,7 @@ class ResetController(implicit p: Parameters) extends NastiModule()(p) {
io.nasti.aw.ready := w_state === w_addr io.nasti.aw.ready := w_state === w_addr
io.nasti.w.ready := w_state === w_data io.nasti.w.ready := w_state === w_data
io.nasti.b.valid := w_state === w_resp && timer === UInt(0) io.nasti.b.valid := w_state === w_resp && timer === 0.U
io.nasti.b.bits := NastiWriteResponseChannel(id = writeId) io.nasti.b.bits := NastiWriteResponseChannel(id = writeId)
io.sys_reset := reg_reset io.sys_reset := reg_reset
@ -138,9 +138,9 @@ class NastiFIFO(implicit p: Parameters) extends NastiModule()(p) {
val outq = Module(new Queue(UInt(w.W), depth)) val outq = Module(new Queue(UInt(w.W), depth))
val inq = Module(new Queue(UInt(w.W), depth)) val inq = Module(new Queue(UInt(w.W), depth))
val writing = Reg(init = Bool(false)) val writing = Reg(init = false.B)
val reading = Reg(init = Bool(false)) val reading = Reg(init = false.B)
val responding = Reg(init = Bool(false)) val responding = Reg(init = false.B)
val len = Reg(UInt(nastiXLenBits.W)) val len = Reg(UInt(nastiXLenBits.W))
val bid = Reg(UInt(nastiXIdBits.W)) val bid = Reg(UInt(nastiXIdBits.W))
val rid = Reg(UInt(nastiXIdBits.W)) val rid = Reg(UInt(nastiXIdBits.W))
@ -156,8 +156,8 @@ class NastiFIFO(implicit p: Parameters) extends NastiModule()(p) {
val raddr = Reg(araddr) val raddr = Reg(araddr)
val waddr = Reg(awaddr) val waddr = Reg(awaddr)
inq.io.enq.valid := io.nasti.w.valid && writing && (waddr === UInt(2)) inq.io.enq.valid := io.nasti.w.valid && writing && (waddr === 2.U)
io.nasti.w.ready := (inq.io.enq.ready || waddr =/= UInt(2)) && writing io.nasti.w.ready := (inq.io.enq.ready || waddr =/= 2.U) && writing
inq.io.enq.bits := io.nasti.w.bits.data inq.io.enq.bits := io.nasti.w.bits.data
/** /**
@ -167,15 +167,15 @@ class NastiFIFO(implicit p: Parameters) extends NastiModule()(p) {
* 0x08 - in FIFO data * 0x08 - in FIFO data
* 0x0C - in FIFO space available (words) * 0x0C - in FIFO space available (words)
*/ */
io.nasti.r.valid := reading && (raddr =/= UInt(0) || outq.io.deq.valid) io.nasti.r.valid := reading && (raddr =/= 0.U || outq.io.deq.valid)
outq.io.deq.ready := reading && raddr === UInt(0) && io.nasti.r.ready outq.io.deq.ready := reading && raddr === 0.U && io.nasti.r.ready
io.nasti.r.bits := NastiReadDataChannel( io.nasti.r.bits := NastiReadDataChannel(
id = rid, id = rid,
data = MuxLookup(raddr, UInt(0), Seq( data = MuxLookup(raddr, 0.U, Seq(
UInt(0) -> outq.io.deq.bits, 0.U -> outq.io.deq.bits,
UInt(1) -> outq.io.count, 1.U -> outq.io.count,
UInt(3) -> (UInt(depth) - inq.io.count))), 3.U -> (depth.U - inq.io.count))),
last = len === UInt(0)) last = len === 0.U)
io.nasti.aw.ready := !writing && !responding io.nasti.aw.ready := !writing && !responding
io.nasti.ar.ready := !reading io.nasti.ar.ready := !reading
@ -183,33 +183,33 @@ class NastiFIFO(implicit p: Parameters) extends NastiModule()(p) {
io.nasti.b.bits := NastiWriteResponseChannel( io.nasti.b.bits := NastiWriteResponseChannel(
id = bid, id = bid,
// writing to anything other that the in FIFO is an error // writing to anything other that the in FIFO is an error
resp = Mux(waddr === UInt(2), RESP_OKAY, RESP_SLVERR)) resp = Mux(waddr === 2.U, RESP_OKAY, RESP_SLVERR))
when (io.nasti.aw.fire()) { when (io.nasti.aw.fire()) {
writing := Bool(true) writing := true.B
waddr := awaddr waddr := awaddr
bid := io.nasti.aw.bits.id bid := io.nasti.aw.bits.id
} }
when (io.nasti.w.fire() && io.nasti.w.bits.last) { when (io.nasti.w.fire() && io.nasti.w.bits.last) {
writing := Bool(false) writing := false.B
responding := Bool(true) responding := true.B
} }
when (io.nasti.b.fire()) { responding := Bool(false) } when (io.nasti.b.fire()) { responding := false.B }
when (io.nasti.ar.fire()) { when (io.nasti.ar.fire()) {
len := io.nasti.ar.bits.len len := io.nasti.ar.bits.len
rid := io.nasti.ar.bits.id rid := io.nasti.ar.bits.id
raddr := araddr raddr := araddr
reading := Bool(true) reading := true.B
} }
when (io.nasti.r.fire()) { when (io.nasti.r.fire()) {
len := len - UInt(1) len := len - 1.U
when (len === UInt(0)) { reading := Bool(false) } when (len === 0.U) { reading := false.B }
} }
def addressOK(chan: NastiAddressChannel): Bool = def addressOK(chan: NastiAddressChannel): Bool =
(chan.len === UInt(0) || chan.burst === BURST_FIXED) && (chan.len === 0.U || chan.burst === BURST_FIXED) &&
chan.size === UInt(log2Up(w/8)) && chan.size === log2Up(w/8).U &&
chan.addr(log2Up(nastiWStrobeBits)-1, 0) === UInt(0) chan.addr(log2Up(nastiWStrobeBits)-1, 0) === 0.U
def dataOK(chan: NastiWriteDataChannel): Bool = def dataOK(chan: NastiWriteDataChannel): Bool =
chan.strb(w/8-1, 0).andR chan.strb(w/8-1, 0).andR

2
testchipip

@ -1 +1 @@
Subproject commit 69b66e4b1d893672d3c6f2fa3797394f391c096c Subproject commit 4b6fe076cfab3c685fd6201559221cbad858c77e