From 46838fd2f055152b515fb367d4b4b75b7844ee0d Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 27 Feb 2017 10:08:22 -0800 Subject: [PATCH] Fixes #39 Make NastiFIFO chisel3 conformant --- common/src/main/scala/Top.scala | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/common/src/main/scala/Top.scala b/common/src/main/scala/Top.scala index 79dae8a..3f734d6 100644 --- a/common/src/main/scala/Top.scala +++ b/common/src/main/scala/Top.scala @@ -128,10 +128,10 @@ class NastiFIFO(implicit p: Parameters) extends NastiModule()(p) { val w = p(SerialInterfaceWidth) val depth = p(SerialFIFODepth) - val io = new Bundle { - val nasti = new NastiIO().flip - val serial = new SerialIO(w).flip - } + val io = IO(new Bundle { + val nasti = Flipped(new NastiIO()) + val serial = Flipped(new SerialIO(w)) + }) require(nastiXDataBits == 32) require(nastiXDataBits == w) @@ -153,8 +153,8 @@ class NastiFIFO(implicit p: Parameters) extends NastiModule()(p) { val addrMSB = addrLSB + log2Up(nRegisters) - 1 val araddr = io.nasti.ar.bits.addr(addrMSB, addrLSB) val awaddr = io.nasti.aw.bits.addr(addrMSB, addrLSB) - val raddr = Reg(araddr) - val waddr = Reg(awaddr) + val raddr = Reg(araddr.cloneType) + val waddr = Reg(awaddr.cloneType) inq.io.enq.valid := io.nasti.w.valid && writing && (waddr === 2.U) io.nasti.w.ready := (inq.io.enq.ready || waddr =/= 2.U) && writing