Add a top level zynq project and link against RC
This commit is contained in:
David Biancolin
parent
0b3237681b
commit
3ca6ba6f94
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@ -1,15 +1,19 @@
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*.log
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*.jou
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*.Xil
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*.swp
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common/build
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common/target
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common/project/target
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common/lib
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common/bootrom
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zedboard/zedboard_rocketchip_*
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zedboard/src/tcl/zedboard_rocketchip_*.tcl
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zedboard/src/tcl/make_bitstream_*.tcl
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zedboard/src/verilog/rocketchip_wrapper.v
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zedboard/src/verilog/Top.*.v
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zedboard/src/verilog/ZynqAdapter.*.v
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zedboard/deliver_output
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zedboard/soft_build
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@ -18,7 +22,6 @@ zybo/src/tcl/zybo_rocketchip_*.tcl
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zybo/src/tcl/make_bitstream_*.tcl
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zybo/src/verilog/rocketchip_wrapper.v
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zybo/src/verilog/Top.*.v
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zybo/src/verilog/ZynqAdapter.*.v
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zybo/deliver_output
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zybo/soft_build
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@ -27,6 +30,5 @@ zc706/src/tcl/zc706_rocketchip_*.tcl
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zc706/src/tcl/make_bitstream_*.tcl
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zc706/src/verilog/rocketchip_wrapper.v
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zc706/src/verilog/Top.*.v
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zc706/src/verilog/ZynqAdapter.*.v
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zc706/deliver_output
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zc706/soft_build
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@ -15,3 +15,6 @@
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[submodule "zc706/fpga-images-zc706"]
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path = zc706/fpga-images-zc706
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url = https://github.com/ucb-bar/fpga-images-zc706.git
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[submodule "rocket-chip"]
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path = rocket-chip
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url = https://github.com/ucb-bar/rocket-chip.git
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@ -18,11 +18,19 @@ verilog_srcs = \
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src/verilog/clocking.vh \
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src/verilog/rocketchip_wrapper.v \
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src/verilog/Top.$(CONFIG).v \
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src/verilog/ZynqAdapter.$(CONFIG).v \
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default: project
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# Taken from rocket chip 2a5aeea. TODO: Maybe source this directly from makefrag?
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SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKET_DIR)/sbt-launch.jar
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FIRRTL_JAR ?= $(ROCKET_DIR)/firrtl/utils/bin/firrtl.jar
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FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver
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$(FIRRTL_JAR): $(@shell find $(ROCKET_DIR)/firrtl/src/main/scala -iname "*.scala")
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$(MAKE) -C $(ROCKET_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKET_DIR)/firrtl build-scala
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CHISEL_ARGS := --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(common_build)
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# Specialize sources for board
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# ------------------------------------------------------------------------------
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@ -37,14 +45,29 @@ src/tcl/make_bitstream_$(CONFIG).tcl: $(common)/make_bitstream.tcl
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sed 's/BOARD_NAME_HERE/$(BOARD)/g;s/CHISEL_CONFIG_HERE/$(CONFIG)/g' \
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$(common)/make_bitstream.tcl > src/tcl/make_bitstream_$(CONFIG).tcl
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src/verilog/ZynqAdapter.$(CONFIG).v:
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cp $(common)/ZynqAdapter.DefaultFPGAConfig.v $@
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# TODO: Can we pass this as an argument to the generator, instead of having
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# to put the bootrom in a specific place?
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$(common)/bootrom:
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ln -s $(ROCKET_DIR)/bootrom $(common)/bootrom
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rocket:
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cd $(ROCKET_DIR)/fsim; \
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make verilog CONFIG=$(CONFIG); \
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cp $(common_build)/Top.$(CONFIG).v $(base_dir)/$(BOARD)/src/verilog
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# TODO: Need a clever way of knowing when to repack rocketchip
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$(common)/lib:
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cd $(ROCKET_DIR) && sbt pack
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mkdir -p $(common)/lib
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cp $(ROCKET_DIR)/target/pack/lib/* $(common)/lib
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$(common_build)/Top.$(CONFIG).fir: $(common)/lib $(common)/bootrom
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mkdir -p $(@D)
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cd $(common) && $(SBT) "run zynq Top $(CONFIG) $(CHISEL_ARGS)"
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mv $(common_build)/Top.fir $@
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$(common_build)/Top.$(CONFIG).v: $(common_build)/Top.$(CONFIG).fir $(FIRRTL_JAR)
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$(FIRRTL) -i $< -o $@ -X verilog
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src/verilog/Top.$(CONFIG).v: $(common_build)/Top.$(CONFIG).v
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cp $< $@
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rocket: src/verilog/Top.$(CONFIG).v
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# Project generation
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@ -0,0 +1,14 @@
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import sbt._
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import Keys._
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object BuildSettings extends Build {
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override lazy val settings = super.settings ++ Seq(
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organization := "berkeley",
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version := "1.2",
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scalaVersion := "2.11.7",
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parallelExecution in Global := false,
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traceLevel := 15,
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scalacOptions ++= Seq("-deprecation","-unchecked")
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)
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lazy val zynq = (project in file("."))
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}
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@ -133,17 +133,6 @@ module rocketchip_wrapper
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wire S_AXI_rlast;
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wire reset, reset_cpu;
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wire debug_req_ready;
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wire debug_req_valid;
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wire [4:0] debug_req_bits_addr;
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wire [1:0] debug_req_bits_op;
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wire [33:0] debug_req_bits_data;
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wire debug_resp_ready;
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wire debug_resp_valid;
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wire [1:0] debug_resp_bits_resp;
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wire [33:0] debug_resp_bits_data;
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wire host_clk;
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wire gclk_i, gclk_fbout, host_clk_i, mmcm_locked;
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@ -265,65 +254,6 @@ module rocketchip_wrapper
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assign reset = !FCLK_RESET0_N || !mmcm_locked;
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ZynqAdapter adapter (
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.clk (host_clk),
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.reset (reset),
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.io_reset(reset_cpu),
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.io_debug_req_ready(debug_req_ready),
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.io_debug_req_valid(debug_req_valid),
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.io_debug_req_bits_addr(debug_req_bits_addr),
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.io_debug_req_bits_op(debug_req_bits_op),
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.io_debug_req_bits_data(debug_req_bits_data),
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.io_debug_resp_ready(debug_resp_ready),
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.io_debug_resp_valid(debug_resp_valid),
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.io_debug_resp_bits_resp(debug_resp_bits_resp),
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.io_debug_resp_bits_data(debug_resp_bits_data),
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.io_nasti_aw_ready (M_AXI_awready),
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.io_nasti_aw_valid (M_AXI_awvalid),
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.io_nasti_aw_bits_addr (M_AXI_awaddr),
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.io_nasti_aw_bits_len (M_AXI_awlen),
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.io_nasti_aw_bits_size (M_AXI_awsize),
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.io_nasti_aw_bits_burst (M_AXI_awburst),
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.io_nasti_aw_bits_id (M_AXI_awid),
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.io_nasti_aw_bits_lock (),
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.io_nasti_aw_bits_prot (),
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.io_nasti_aw_bits_qos (),
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.io_nasti_aw_bits_region (),
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.io_nasti_ar_ready (M_AXI_arready),
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.io_nasti_ar_valid (M_AXI_arvalid),
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.io_nasti_ar_bits_addr (M_AXI_araddr),
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.io_nasti_ar_bits_len (M_AXI_arlen),
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.io_nasti_ar_bits_size (M_AXI_arsize),
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.io_nasti_ar_bits_burst (M_AXI_arburst),
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.io_nasti_ar_bits_id (M_AXI_arid),
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.io_nasti_ar_bits_lock (),
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.io_nasti_ar_bits_prot (),
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.io_nasti_ar_bits_qos (),
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.io_nasti_ar_bits_region (),
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.io_nasti_w_valid (M_AXI_wvalid),
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.io_nasti_w_ready (M_AXI_wready),
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.io_nasti_w_bits_data (M_AXI_wdata),
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.io_nasti_w_bits_strb (M_AXI_wstrb),
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.io_nasti_w_bits_last (M_AXI_wlast),
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.io_nasti_r_valid (M_AXI_rvalid),
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.io_nasti_r_ready (M_AXI_rready),
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.io_nasti_r_bits_id (M_AXI_rid),
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.io_nasti_r_bits_resp (M_AXI_rresp),
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.io_nasti_r_bits_data (M_AXI_rdata),
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.io_nasti_r_bits_last (M_AXI_rlast),
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.io_nasti_b_valid (M_AXI_bvalid),
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.io_nasti_b_ready (M_AXI_bready),
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.io_nasti_b_bits_id (M_AXI_bid),
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.io_nasti_b_bits_resp (M_AXI_bresp)
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);
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wire [31:0] mem_araddr;
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wire [31:0] mem_awaddr;
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@ -333,9 +263,50 @@ module rocketchip_wrapper
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Top top(
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.clk(host_clk),
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.reset(reset_cpu),
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.io_interrupts_0(1'b0),
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.io_interrupts_1(1'b0),
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.reset(reset),
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.io_ps_axi_slave_aw_ready (M_AXI_awready),
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.io_ps_axi_slave_aw_valid (M_AXI_awvalid),
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.io_ps_axi_slave_aw_bits_addr (M_AXI_awaddr),
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.io_ps_axi_slave_aw_bits_len (M_AXI_awlen),
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.io_ps_axi_slave_aw_bits_size (M_AXI_awsize),
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.io_ps_axi_slave_aw_bits_burst (M_AXI_awburst),
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.io_ps_axi_slave_aw_bits_id (M_AXI_awid),
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.io_ps_axi_slave_aw_bits_lock (),
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.io_ps_axi_slave_aw_bits_prot (),
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.io_ps_axi_slave_aw_bits_qos (),
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.io_ps_axi_slave_aw_bits_region (),
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.io_ps_axi_slave_ar_ready (M_AXI_arready),
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.io_ps_axi_slave_ar_valid (M_AXI_arvalid),
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.io_ps_axi_slave_ar_bits_addr (M_AXI_araddr),
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.io_ps_axi_slave_ar_bits_len (M_AXI_arlen),
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.io_ps_axi_slave_ar_bits_size (M_AXI_arsize),
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.io_ps_axi_slave_ar_bits_burst (M_AXI_arburst),
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.io_ps_axi_slave_ar_bits_id (M_AXI_arid),
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.io_ps_axi_slave_ar_bits_lock (),
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.io_ps_axi_slave_ar_bits_prot (),
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.io_ps_axi_slave_ar_bits_qos (),
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.io_ps_axi_slave_ar_bits_region (),
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.io_ps_axi_slave_w_valid (M_AXI_wvalid),
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.io_ps_axi_slave_w_ready (M_AXI_wready),
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.io_ps_axi_slave_w_bits_data (M_AXI_wdata),
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.io_ps_axi_slave_w_bits_strb (M_AXI_wstrb),
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.io_ps_axi_slave_w_bits_last (M_AXI_wlast),
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.io_ps_axi_slave_r_valid (M_AXI_rvalid),
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.io_ps_axi_slave_r_ready (M_AXI_rready),
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.io_ps_axi_slave_r_bits_id (M_AXI_rid),
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.io_ps_axi_slave_r_bits_resp (M_AXI_rresp),
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.io_ps_axi_slave_r_bits_data (M_AXI_rdata),
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.io_ps_axi_slave_r_bits_last (M_AXI_rlast),
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.io_ps_axi_slave_b_valid (M_AXI_bvalid),
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.io_ps_axi_slave_b_ready (M_AXI_bready),
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.io_ps_axi_slave_b_bits_id (M_AXI_bid),
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.io_ps_axi_slave_b_bits_resp (M_AXI_bresp),
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.io_mem_axi_0_ar_valid (S_AXI_arvalid),
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.io_mem_axi_0_ar_ready (S_AXI_arready),
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.io_mem_axi_0_ar_bits_addr (mem_araddr),
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@ -374,16 +345,7 @@ module rocketchip_wrapper
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.io_mem_axi_0_r_bits_resp (S_AXI_rresp),
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.io_mem_axi_0_r_bits_id (S_AXI_rid),
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.io_mem_axi_0_r_bits_data (S_AXI_rdata),
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.io_mem_axi_0_r_bits_last (S_AXI_rlast),
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.io_debug_req_ready(debug_req_ready),
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.io_debug_req_valid(debug_req_valid),
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.io_debug_req_bits_addr(debug_req_bits_addr),
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.io_debug_req_bits_op(debug_req_bits_op),
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.io_debug_req_bits_data(debug_req_bits_data),
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.io_debug_resp_ready(debug_resp_ready),
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.io_debug_resp_valid(debug_resp_valid),
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.io_debug_resp_bits_resp(debug_resp_bits_resp),
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.io_debug_resp_bits_data(debug_resp_bits_data)
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.io_mem_axi_0_r_bits_last (S_AXI_rlast)
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);
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`ifndef differential_clock
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IBUFG ibufg_gclk (.I(clk), .O(gclk_i));
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@ -1,3 +1,4 @@
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package zynq
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import scala.math.min
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@ -6,7 +7,7 @@ import uncore.tilelink._
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import junctions._
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import cde.Parameters
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import uncore.devices.{DebugBusIO, DebugBusReq, DebugBusResp, DMKey}
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import uncore.devices.DbBusConsts
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import uncore.devices.DbBusConsts._
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/* TODO: This module should be instantiated by a top-level project that also
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* instantiates rocket-chip.
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@ -44,7 +45,6 @@ class ZynqAdapter(implicit val p: Parameters)
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val RESP_ADDR = 0x10
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val RESET_ADDR = 0x20
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import DbBusConsts._
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val debugAddrSize = p(DMKey).nDebugBusAddrSize
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val reqOffset = dbDataSize
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val opOffset = dbDataSize
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@ -0,0 +1,76 @@
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package zynq
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import Chisel._
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import junctions._
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import cde.{Parameters, Config, CDEMatchError}
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import rocketchip._
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import uncore.devices.{DebugBusIO}
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class Top(implicit val p: Parameters) extends Module
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with HasTopLevelParameters {
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val adapterParams = p.alterPartial({
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case NastiKey => NastiParameters(
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dataBits = 32,
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addrBits = 32,
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idBits = 12)
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})
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val io = new Bundle {
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val ps_axi_slave = new NastiIO()(adapterParams).flip
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val mem_axi = Vec(nMemAXIChannels, new NastiIO)
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}
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val adapter = Module(new ZynqAdapter()(adapterParams))
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val rocket = Module(new rocketchip.Top(p))
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adapter.io.nasti <> io.ps_axi_slave
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rocket.reset := adapter.io.reset
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rocket.io.debug <> adapter.io.debug
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io.mem_axi <> rocket.io.mem_axi
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rocket.io.interrupts map(_ := Bool(false))
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}
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/* Would like to disable interrupts in zynq configurations
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class ZynqConfig extends Config(
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(pname, site, here) => pname match {
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case NExtInterrupts => 0
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case _ => throw new CDEMatchError
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})
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*/
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// Do this to avoid looking up the config in a second (in this case, RC) project
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class DefaultFPGAConfig extends Config(new rocketchip.DefaultFPGAConfig)
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class DefaultFPGASmallConfig extends Config(new rocketchip.DefaultFPGASmallConfig)
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// This copied directly from rocketchip 2a5aeea
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// Could invoke RC main directly, but don't want all the test generation
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object Generator extends App {
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val projectName = args(0)
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val topModuleName = args(1)
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val configClassName = args(2)
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val aggregateConfigs = configClassName.split('_')
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val finalConfig = aggregateConfigs.foldRight(new Config()) { case (currentConfigName, finalConfig) =>
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val currentConfig = try {
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Class.forName(s"$projectName.$currentConfigName").newInstance.asInstanceOf[Config]
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} catch {
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case e: java.lang.ClassNotFoundException =>
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throwException("Unable to find part \"" + currentConfigName +
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"\" of configClassName \"" + configClassName +
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"\", did you misspell it?", e)
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}
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currentConfig ++ finalConfig
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}
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val world = finalConfig.toInstance
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val paramsFromConfig: Parameters = Parameters.root(world)
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val gen = () =>
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Class.forName(s"$projectName.$topModuleName")
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.getConstructor(classOf[cde.Parameters])
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.newInstance(paramsFromConfig)
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.asInstanceOf[Module]
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chiselMain.run(args.drop(3), gen)
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}
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@ -91,7 +91,6 @@ set obj [get_filesets sources_1]
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set files [list \
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"[file normalize "$origin_dir/src/verilog/clocking.vh"]"\
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"[file normalize "$origin_dir/src/verilog/Top.CHISEL_CONFIG_HERE.v"]"\
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"[file normalize "$origin_dir/src/verilog/ZynqAdapter.CHISEL_CONFIG_HERE.v"]"\
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"[file normalize "$origin_dir/src/verilog/rocketchip_wrapper.v"]"\
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]
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add_files -norecurse -fileset $obj $files
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@ -1 +0,0 @@
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..
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@ -0,0 +1 @@
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Subproject commit 2906c7516739f2eed1299bb07457583fa1fdcbc4
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Reference in New Issue