upgrading common and zedboard to vivado 2014.2
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@ -1,10 +1,10 @@
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#
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# Vivado (TM) v2013.4 (64-bit)
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# Vivado (TM) v2014.2 (64-bit)
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#
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# BOARD_NAME_HERE_rocketchip.tcl: Tcl script for re-creating project 'BOARD_NAME_HERE_rocketchip'
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#
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# Generated by Vivado on Fri Aug 01 10:36:13 PDT 2014
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# IP Build 208076 on Mon Dec 2 12:38:17 MST 2013
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# Generated by Vivado on Fri Sep 12 16:05:06 PDT 2014
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# IP Build 924643 on Fri May 30 09:20:16 MDT 2014
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#
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# This file contains the Vivado Tcl commands for re-creating the project to the state*
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# when this script was generated. In order to re-create the project, please source this
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@ -14,8 +14,11 @@
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# original project, however they will not be launched automatically. To regenerate the
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# run results please launch the synthesis/implementation runs as needed.
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# Set the original project directory path for adding/importing sources in the new project
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set orig_proj_dir "./BOARD_NAME_HERE_rocketchip"
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# Set the reference directory for source file relative paths (by default the value is script directory path)
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set origin_dir "."
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# Set the directory path for the original project from where this script was exported
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set orig_proj_dir "[file normalize "$origin_dir/BOARD_NAME_HERE_rocketchip"]"
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# Create project
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create_project BOARD_NAME_HERE_rocketchip $orig_proj_dir
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@ -25,22 +28,24 @@ set proj_dir [get_property directory [current_project]]
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# Set project properties
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set obj [get_projects BOARD_NAME_HERE_rocketchip]
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set_property "default_lib" "xil_defaultlib" $obj
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set_property "part" "PART_NUMBER_HERE" $obj
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# REPLACE FOR OFFICIAL BOARD NAME $obj
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set_property "simulator_language" "Mixed" $obj
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# Create 'sources_1' fileset (if not found)
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if {[string equal [get_filesets sources_1] ""]} {
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if {[string equal [get_filesets -quiet sources_1] ""]} {
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create_fileset -srcset sources_1
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}
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# Import local files from the original project
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# Set 'sources_1' fileset object
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set obj [get_filesets sources_1]
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set files [list \
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"[file normalize "$orig_proj_dir/../src/verilog/Top.DefaultFPGAConfig.v"]"\
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"[file normalize "$orig_proj_dir/../src/verilog/rocketchip_wrapper.v"]"\
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"[file normalize "$orig_proj_dir/../src/verilog/clocking.vh"]"\
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"[file normalize "$origin_dir/src/verilog/clocking.vh"]"\
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"[file normalize "$origin_dir/src/verilog/Top.DefaultFPGAConfig.v"]"\
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"[file normalize "$origin_dir/src/verilog/rocketchip_wrapper.v"]"\
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]
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set imported_files [import_files -fileset sources_1 $files]
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add_files -norecurse -fileset $obj $files
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# Set 'sources_1' fileset file properties for remote files
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# None
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@ -53,34 +58,31 @@ set obj [get_filesets sources_1]
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set_property "top" "rocketchip_wrapper" $obj
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# Create 'constrs_1' fileset (if not found)
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if {[string equal [get_filesets constrs_1] ""]} {
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if {[string equal [get_filesets -quiet constrs_1] ""]} {
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create_fileset -constrset constrs_1
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}
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# Add files to 'constrs_1' fileset
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# Set 'constrs_1' fileset object
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set obj [get_filesets constrs_1]
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set files [list \
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"[file normalize "$orig_proj_dir/../src/constrs/base.xdc"]"\
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]
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add_files -norecurse -fileset $obj $files
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# Set 'constrs_1' fileset file properties for remote files
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set file "$orig_proj_dir/../src/constrs/base.xdc"
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# Add/Import constrs file and set constrs file properties
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set file "[file normalize "$origin_dir/src/constrs/base.xdc"]"
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set file_added [add_files -norecurse -fileset $obj $file]
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set file "$origin_dir/src/constrs/base.xdc"
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set file [file normalize $file]
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set file_obj [get_files -of_objects constrs_1 [list "*$file"]]
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set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
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set_property "file_type" "XDC" $file_obj
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# Set 'constrs_1' fileset properties
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set obj [get_filesets constrs_1]
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set_property "target_constrs_file" "$orig_proj_dir/../src/constrs/base.xdc" $obj
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set_property "target_constrs_file" "[file normalize "$origin_dir/src/constrs/base.xdc"]" $obj
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# Create 'sim_1' fileset (if not found)
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if {[string equal [get_filesets sim_1] ""]} {
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if {[string equal [get_filesets -quiet sim_1] ""]} {
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create_fileset -simset sim_1
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}
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# Add files to 'sim_1' fileset
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# Set 'sim_1' fileset object
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set obj [get_filesets sim_1]
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# Empty (no sources present)
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@ -89,16 +91,16 @@ set obj [get_filesets sim_1]
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set_property "top" "rocketchip_wrapper" $obj
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# Create 'synth_1' run (if not found)
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if {[string equal [get_runs synth_1] ""]} {
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create_run -name synth_1 -part PART_NUMBER_HERE -flow {Vivado Synthesis 2013} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
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if {[string equal [get_runs -quiet synth_1] ""]} {
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create_run -name synth_1 -part PART_NUMBER_HERE -flow {Vivado Synthesis 2014} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
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}
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set obj [get_runs synth_1]
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set_property "needs_refresh" "1" $obj
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set_property "part" "PART_NUMBER_HERE" $obj
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# Create 'impl_1' run (if not found)
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if {[string equal [get_runs impl_1] ""]} {
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create_run -name impl_1 -part PART_NUMBER_HERE -flow {Vivado Implementation 2013} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
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if {[string equal [get_runs -quiet impl_1] ""]} {
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create_run -name impl_1 -part PART_NUMBER_HERE -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
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}
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set obj [get_runs impl_1]
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set_property "needs_refresh" "1" $obj
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