Update readme to include deprecation note.

This commit is contained in:
David Biancolin 2018-04-20 15:25:12 -04:00 committed by GitHub
parent 94893f1d62
commit 040a8ad2ac
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 2 additions and 0 deletions

View File

@ -1,5 +1,7 @@
Rocket Chip on Zynq FPGAs
=========================
### Warning: This repository is deprecated and does not track Rocket Chip master.
#### Those looking for an FPGA prototype of Rocket Chip should checkout SiFives [Freedom platform](https://github.com/sifive/freedom). Those looking for an FPGA-accelerated simulation environment should see [FireSim](https://fires.im/) ([repo, TBR](https://github.com/firesim/firesim)) which will be released in the Summer
This repository contains the files needed to run the RISC-V [rocket chip](https://github.com/ucb-bar/rocket-chip) on
various Zynq FPGA boards ([Zybo](http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1198&Prod=ZYBO), [Zedboard](http://zedboard.org/product/zedboard), [ZC706](http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm)) with Vivado 2016.2. Efforts have been made to not only automate the process of generating files for these boards, but to also reduce duplication as well as the size of this repo. Prebuilt images are available in git submodules, and they are only shallowly cloned if requested.