make project default target
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parent
213537f42f
commit
00267721d3
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@ -12,6 +12,10 @@ verilog_srcs = \
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src/verilog/Top.DefaultFPGAConfig.v \
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src/verilog/Top.DefaultFPGAConfig.v \
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default: project
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# Specialize sources for board
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# Specialize sources for board
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src/verilog/rocketchip_wrapper.v: $(base_dir)/common/rocketchip_wrapper.v
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src/verilog/rocketchip_wrapper.v: $(base_dir)/common/rocketchip_wrapper.v
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cp $(base_dir)/common/rocketchip_wrapper.v src/verilog/
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cp $(base_dir)/common/rocketchip_wrapper.v src/verilog/
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@ -23,6 +27,7 @@ src/tcl/make_bitstream.tcl: $(base_dir)/common/make_bitstream.tcl
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sed 's/BOARD_NAME_HERE/$(BOARD)/g' $(base_dir)/common/make_bitstream.tcl > src/tcl/make_bitstream.tcl
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sed 's/BOARD_NAME_HERE/$(BOARD)/g' $(base_dir)/common/make_bitstream.tcl > src/tcl/make_bitstream.tcl
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# Project generation
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# Project generation
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$(BOARD)_rocketchip/$(BOARD)_rocketchip.xpr: src/verilog/rocketchip_wrapper.v src/tcl/$(BOARD)_rocketchip.tcl
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$(BOARD)_rocketchip/$(BOARD)_rocketchip.xpr: src/verilog/rocketchip_wrapper.v src/tcl/$(BOARD)_rocketchip.tcl
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vivado -mode tcl -source src/tcl/$(BOARD)_rocketchip.tcl
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vivado -mode tcl -source src/tcl/$(BOARD)_rocketchip.tcl
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@ -30,6 +35,14 @@ $(BOARD)_rocketchip/$(BOARD)_rocketchip.xpr: src/verilog/rocketchip_wrapper.v sr
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$(BOARD)_rocketchip/$(BOARD)_rocketchip.runs/impl_1/rocketchip_wrapper.bit: $(BOARD)_rocketchip/$(BOARD)_rocketchip.xpr src/tcl/make_bitstream.tcl $(verilog_srcs) src/constrs/base.xdc
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$(BOARD)_rocketchip/$(BOARD)_rocketchip.runs/impl_1/rocketchip_wrapper.bit: $(BOARD)_rocketchip/$(BOARD)_rocketchip.xpr src/tcl/make_bitstream.tcl $(verilog_srcs) src/constrs/base.xdc
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vivado -mode tcl -source src/tcl/make_bitstream.tcl
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vivado -mode tcl -source src/tcl/make_bitstream.tcl
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project: $(BOARD)_rocketchip/$(BOARD)_rocketchip.xpr
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vivado: $(BOARD)_rocketchip/$(BOARD)_rocketchip.xpr
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vivado $(BOARD)_rocketchip/$(BOARD)_rocketchip.xpr &
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bitstream: $(BOARD)_rocketchip/$(BOARD)_rocketchip.runs/impl_1/rocketchip_wrapper.bit
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# Handle git submodule for prebuilt modules
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# Handle git submodule for prebuilt modules
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fpga-images-$(BOARD)/boot.bif:
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fpga-images-$(BOARD)/boot.bif:
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@ -38,25 +51,14 @@ fpga-images-$(BOARD)/boot.bif:
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fpga-images-$(BOARD)/boot.bin: fpga-images-$(BOARD)/boot.bif $(BOARD)_rocketchip/$(BOARD)_rocketchip.runs/impl_1/rocketchip_wrapper.bit
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fpga-images-$(BOARD)/boot.bin: fpga-images-$(BOARD)/boot.bif $(BOARD)_rocketchip/$(BOARD)_rocketchip.runs/impl_1/rocketchip_wrapper.bit
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cd fpga-images-$(BOARD); bootgen -image boot.bif -w -o boot.bin
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cd fpga-images-$(BOARD); bootgen -image boot.bif -w -o boot.bin
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# Virtual targets to provide easier names
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.PHONY: project
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project: $(BOARD)_rocketchip/$(BOARD)_rocketchip.xpr
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.PHONY: vivado
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vivado: $(BOARD)_rocketchip/$(BOARD)_rocketchip.xpr
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vivado $(BOARD)_rocketchip/$(BOARD)_rocketchip.xpr &
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.PHONY: bitstream
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bitstream: $(BOARD)_rocketchip/$(BOARD)_rocketchip.runs/impl_1/rocketchip_wrapper.bit
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.PHONY: fetch-images
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fetch-images: fpga-images-$(BOARD)/boot.bif
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fetch-images: fpga-images-$(BOARD)/boot.bif
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.PHONY: load-sd
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load-sd: fpga-images-$(BOARD)/boot.bin
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load-sd: fpga-images-$(BOARD)/boot.bin
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$(base_dir)/common/load_card.sh $(SD)
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$(base_dir)/common/load_card.sh $(SD)
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.PHONY: clean
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clean:
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clean:
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rm -f *.log *.jou
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rm -f *.log *.jou
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.PHONY: project vivado bitstream fetch-images load-sd clean
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