mirror of https://github.com/rust-lang/rust.git
Auto merge of #101069 - zhaixiaojuan:loongarch64-inline-asm, r=Amanieu
Add loongarch64 asm! support
This commit is contained in:
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commit
999e6e5afb
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@ -593,6 +593,8 @@ fn reg_to_gcc(reg: InlineAsmRegOrRegClass) -> ConstraintOrRegister {
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InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => "r",
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InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => "w",
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InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => "r",
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InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg) => "r",
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InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg) => "f",
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InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg) => "r",
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InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_addr) => "a",
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InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_data) => "d",
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@ -667,6 +669,8 @@ fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegCl
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InlineAsmRegClass::Avr(_) => unimplemented!(),
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InlineAsmRegClass::Bpf(_) => unimplemented!(),
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InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(),
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InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg) => cx.type_i32(),
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InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg) => cx.type_f32(),
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InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg) => cx.type_i32(),
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InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_addr) => cx.type_i32(),
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InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_data) => cx.type_i32(),
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@ -804,6 +808,7 @@ fn modifier_to_gcc(arch: InlineAsmArch, reg: InlineAsmRegClass, modifier: Option
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}
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}
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InlineAsmRegClass::Hexagon(_) => None,
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InlineAsmRegClass::LoongArch(_) => None,
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InlineAsmRegClass::Mips(_) => None,
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InlineAsmRegClass::Nvptx(_) => None,
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InlineAsmRegClass::PowerPC(_) => None,
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@ -236,6 +236,7 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
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InlineAsmArch::Nvptx64 => {}
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InlineAsmArch::PowerPC | InlineAsmArch::PowerPC64 => {}
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InlineAsmArch::Hexagon => {}
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InlineAsmArch::LoongArch64 => {}
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InlineAsmArch::Mips | InlineAsmArch::Mips64 => {}
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InlineAsmArch::S390x => {}
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InlineAsmArch::SpirV => {}
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@ -633,6 +634,8 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'_>>) ->
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InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
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| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => "w",
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InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => "r",
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InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg) => "r",
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InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg) => "f",
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InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => "r",
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InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => "f",
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InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => "h",
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@ -719,6 +722,7 @@ fn modifier_to_llvm(
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}
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}
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InlineAsmRegClass::Hexagon(_) => None,
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InlineAsmRegClass::LoongArch(_) => None,
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InlineAsmRegClass::Mips(_) => None,
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InlineAsmRegClass::Nvptx(_) => None,
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InlineAsmRegClass::PowerPC(_) => None,
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@ -803,6 +807,8 @@ fn dummy_output_type<'ll>(cx: &CodegenCx<'ll, '_>, reg: InlineAsmRegClass) -> &'
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cx.type_vector(cx.type_i64(), 2)
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}
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InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(),
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InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg) => cx.type_i32(),
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InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg) => cx.type_f32(),
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InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => cx.type_i32(),
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InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => cx.type_f32(),
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InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),
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@ -0,0 +1,131 @@
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use super::{InlineAsmArch, InlineAsmType};
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use rustc_macros::HashStable_Generic;
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use rustc_span::Symbol;
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use std::fmt;
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def_reg_class! {
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LoongArch LoongArchInlineAsmRegClass {
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reg,
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freg,
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}
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}
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impl LoongArchInlineAsmRegClass {
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pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
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&[]
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}
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pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
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None
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}
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pub fn suggest_modifier(
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self,
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_arch: InlineAsmArch,
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_ty: InlineAsmType,
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) -> Option<(char, &'static str)> {
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None
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}
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pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
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None
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}
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pub fn supported_types(
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self,
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arch: InlineAsmArch,
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) -> &'static [(InlineAsmType, Option<Symbol>)] {
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match (self, arch) {
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(Self::reg, InlineAsmArch::LoongArch64) => types! { _: I8, I16, I32, I64, F32, F64; },
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(Self::reg, _) => types! { _: I8, I16, I32, F32; },
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(Self::freg, _) => types! { _: F32, F64; },
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}
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}
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}
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// The reserved registers are taken from <https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp#79>
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def_regs! {
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LoongArch LoongArchInlineAsmReg LoongArchInlineAsmRegClass {
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r1: reg = ["$r1","$ra"],
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r4: reg = ["$r4","$a0"],
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r5: reg = ["$r5","$a1"],
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r6: reg = ["$r6","$a2"],
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r7: reg = ["$r7","$a3"],
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r8: reg = ["$r8","$a4"],
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r9: reg = ["$r9","$a5"],
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r10: reg = ["$r10","$a6"],
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r11: reg = ["$r11","$a7"],
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r12: reg = ["$r12","$t0"],
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r13: reg = ["$r13","$t1"],
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r14: reg = ["$r14","$t2"],
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r15: reg = ["$r15","$t3"],
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r16: reg = ["$r16","$t4"],
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r17: reg = ["$r17","$t5"],
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r18: reg = ["$r18","$t6"],
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r19: reg = ["$r19","$t7"],
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r20: reg = ["$r20","$t8"],
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r23: reg = ["$r23","$s0"],
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r24: reg = ["$r24","$s1"],
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r25: reg = ["$r25","$s2"],
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r26: reg = ["$r26","$s3"],
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r27: reg = ["$r27","$s4"],
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r28: reg = ["$r28","$s5"],
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r29: reg = ["$r29","$s6"],
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r30: reg = ["$r30","$s7"],
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f0: freg = ["$f0","$fa0"],
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f1: freg = ["$f1","$fa1"],
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f2: freg = ["$f2","$fa2"],
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f3: freg = ["$f3","$fa3"],
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f4: freg = ["$f4","$fa4"],
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f5: freg = ["$f5","$fa5"],
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f6: freg = ["$f6","$fa6"],
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f7: freg = ["$f7","$fa7"],
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f8: freg = ["$f8","$ft0"],
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f9: freg = ["$f9","$ft1"],
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f10: freg = ["$f10","$ft2"],
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f11: freg = ["$f11","$ft3"],
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f12: freg = ["$f12","$ft4"],
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f13: freg = ["$f13","$ft5"],
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f14: freg = ["$f14","$ft6"],
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f15: freg = ["$f15","$ft7"],
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f16: freg = ["$f16","$ft8"],
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f17: freg = ["$f17","$ft9"],
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f18: freg = ["$f18","$ft10"],
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f19: freg = ["$f19","$ft11"],
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f20: freg = ["$f20","$ft12"],
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f21: freg = ["$f21","$ft13"],
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f22: freg = ["$f22","$ft14"],
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f23: freg = ["$f23","$ft15"],
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f24: freg = ["$f24","$fs0"],
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f25: freg = ["$f25","$fs1"],
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f26: freg = ["$f26","$fs2"],
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f27: freg = ["$f27","$fs3"],
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f28: freg = ["$f28","$fs4"],
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f29: freg = ["$f29","$fs5"],
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f30: freg = ["$f30","$fs6"],
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f31: freg = ["$f31","$fs7"],
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#error = ["$r0","$zero"] =>
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"constant zero cannot be used as an operand for inline asm",
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#error = ["$r2","$tp"] =>
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"reserved for TLS",
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#error = ["$r3","$sp"] =>
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"the stack pointer cannot be used as an operand for inline asm",
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#error = ["$r21"] =>
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"reserved by the ABI",
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#error = ["$r22","$fp"] =>
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"the frame pointer cannot be used as an operand for inline asm",
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#error = ["$r31","$s8"] =>
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"$r31 is used internally by LLVM and cannot be used as an operand for inline asm",
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}
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}
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impl LoongArchInlineAsmReg {
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pub fn emit(
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self,
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out: &mut dyn fmt::Write,
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_arch: InlineAsmArch,
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_modifier: Option<char>,
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) -> fmt::Result {
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out.write_str(self.name())
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}
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}
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@ -168,6 +168,7 @@ mod arm;
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mod avr;
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mod bpf;
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mod hexagon;
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mod loongarch;
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mod m68k;
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mod mips;
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mod msp430;
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@ -184,6 +185,7 @@ pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass};
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pub use avr::{AvrInlineAsmReg, AvrInlineAsmRegClass};
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pub use bpf::{BpfInlineAsmReg, BpfInlineAsmRegClass};
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pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass};
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pub use loongarch::{LoongArchInlineAsmReg, LoongArchInlineAsmRegClass};
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pub use m68k::{M68kInlineAsmReg, M68kInlineAsmRegClass};
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pub use mips::{MipsInlineAsmReg, MipsInlineAsmRegClass};
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pub use msp430::{Msp430InlineAsmReg, Msp430InlineAsmRegClass};
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@ -205,6 +207,7 @@ pub enum InlineAsmArch {
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RiscV64,
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Nvptx64,
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Hexagon,
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LoongArch64,
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Mips,
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Mips64,
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PowerPC,
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@ -234,6 +237,7 @@ impl FromStr for InlineAsmArch {
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"powerpc" => Ok(Self::PowerPC),
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"powerpc64" => Ok(Self::PowerPC64),
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"hexagon" => Ok(Self::Hexagon),
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"loongarch64" => Ok(Self::LoongArch64),
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"mips" => Ok(Self::Mips),
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"mips64" => Ok(Self::Mips64),
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"s390x" => Ok(Self::S390x),
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@ -259,6 +263,7 @@ pub enum InlineAsmReg {
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Nvptx(NvptxInlineAsmReg),
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PowerPC(PowerPCInlineAsmReg),
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Hexagon(HexagonInlineAsmReg),
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LoongArch(LoongArchInlineAsmReg),
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Mips(MipsInlineAsmReg),
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S390x(S390xInlineAsmReg),
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SpirV(SpirVInlineAsmReg),
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@ -280,6 +285,7 @@ impl InlineAsmReg {
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Self::RiscV(r) => r.name(),
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Self::PowerPC(r) => r.name(),
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Self::Hexagon(r) => r.name(),
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Self::LoongArch(r) => r.name(),
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Self::Mips(r) => r.name(),
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Self::S390x(r) => r.name(),
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Self::Bpf(r) => r.name(),
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@ -298,6 +304,7 @@ impl InlineAsmReg {
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Self::RiscV(r) => InlineAsmRegClass::RiscV(r.reg_class()),
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Self::PowerPC(r) => InlineAsmRegClass::PowerPC(r.reg_class()),
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Self::Hexagon(r) => InlineAsmRegClass::Hexagon(r.reg_class()),
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Self::LoongArch(r) => InlineAsmRegClass::LoongArch(r.reg_class()),
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Self::Mips(r) => InlineAsmRegClass::Mips(r.reg_class()),
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Self::S390x(r) => InlineAsmRegClass::S390x(r.reg_class()),
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Self::Bpf(r) => InlineAsmRegClass::Bpf(r.reg_class()),
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@ -324,6 +331,7 @@ impl InlineAsmReg {
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Self::PowerPC(PowerPCInlineAsmReg::parse(name)?)
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}
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InlineAsmArch::Hexagon => Self::Hexagon(HexagonInlineAsmReg::parse(name)?),
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InlineAsmArch::LoongArch64 => Self::LoongArch(LoongArchInlineAsmReg::parse(name)?),
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InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
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Self::Mips(MipsInlineAsmReg::parse(name)?)
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}
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@ -354,6 +362,9 @@ impl InlineAsmReg {
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Self::RiscV(r) => r.validate(arch, reloc_model, target_features, target, is_clobber),
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Self::PowerPC(r) => r.validate(arch, reloc_model, target_features, target, is_clobber),
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Self::Hexagon(r) => r.validate(arch, reloc_model, target_features, target, is_clobber),
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Self::LoongArch(r) => {
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r.validate(arch, reloc_model, target_features, target, is_clobber)
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}
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Self::Mips(r) => r.validate(arch, reloc_model, target_features, target, is_clobber),
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Self::S390x(r) => r.validate(arch, reloc_model, target_features, target, is_clobber),
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Self::Bpf(r) => r.validate(arch, reloc_model, target_features, target, is_clobber),
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@ -379,6 +390,7 @@ impl InlineAsmReg {
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Self::RiscV(r) => r.emit(out, arch, modifier),
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Self::PowerPC(r) => r.emit(out, arch, modifier),
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Self::Hexagon(r) => r.emit(out, arch, modifier),
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Self::LoongArch(r) => r.emit(out, arch, modifier),
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Self::Mips(r) => r.emit(out, arch, modifier),
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Self::S390x(r) => r.emit(out, arch, modifier),
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Self::Bpf(r) => r.emit(out, arch, modifier),
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@ -397,6 +409,7 @@ impl InlineAsmReg {
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Self::RiscV(_) => cb(self),
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Self::PowerPC(r) => r.overlapping_regs(|r| cb(Self::PowerPC(r))),
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Self::Hexagon(r) => r.overlapping_regs(|r| cb(Self::Hexagon(r))),
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Self::LoongArch(_) => cb(self),
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Self::Mips(_) => cb(self),
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Self::S390x(_) => cb(self),
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Self::Bpf(r) => r.overlapping_regs(|r| cb(Self::Bpf(r))),
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@ -418,6 +431,7 @@ pub enum InlineAsmRegClass {
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Nvptx(NvptxInlineAsmRegClass),
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PowerPC(PowerPCInlineAsmRegClass),
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Hexagon(HexagonInlineAsmRegClass),
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LoongArch(LoongArchInlineAsmRegClass),
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Mips(MipsInlineAsmRegClass),
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S390x(S390xInlineAsmRegClass),
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SpirV(SpirVInlineAsmRegClass),
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@ -440,6 +454,7 @@ impl InlineAsmRegClass {
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Self::Nvptx(r) => r.name(),
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Self::PowerPC(r) => r.name(),
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Self::Hexagon(r) => r.name(),
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Self::LoongArch(r) => r.name(),
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Self::Mips(r) => r.name(),
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Self::S390x(r) => r.name(),
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Self::SpirV(r) => r.name(),
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@ -464,6 +479,7 @@ impl InlineAsmRegClass {
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Self::Nvptx(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Nvptx),
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Self::PowerPC(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::PowerPC),
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Self::Hexagon(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Hexagon),
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Self::LoongArch(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::LoongArch),
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Self::Mips(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Mips),
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Self::S390x(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::S390x),
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Self::SpirV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::SpirV),
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@ -495,6 +511,7 @@ impl InlineAsmRegClass {
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Self::Nvptx(r) => r.suggest_modifier(arch, ty),
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Self::PowerPC(r) => r.suggest_modifier(arch, ty),
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Self::Hexagon(r) => r.suggest_modifier(arch, ty),
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Self::LoongArch(r) => r.suggest_modifier(arch, ty),
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Self::Mips(r) => r.suggest_modifier(arch, ty),
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Self::S390x(r) => r.suggest_modifier(arch, ty),
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Self::SpirV(r) => r.suggest_modifier(arch, ty),
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@ -522,6 +539,7 @@ impl InlineAsmRegClass {
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Self::Nvptx(r) => r.default_modifier(arch),
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Self::PowerPC(r) => r.default_modifier(arch),
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Self::Hexagon(r) => r.default_modifier(arch),
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Self::LoongArch(r) => r.default_modifier(arch),
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Self::Mips(r) => r.default_modifier(arch),
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Self::S390x(r) => r.default_modifier(arch),
|
||||
Self::SpirV(r) => r.default_modifier(arch),
|
||||
|
|
@ -548,6 +566,7 @@ impl InlineAsmRegClass {
|
|||
Self::Nvptx(r) => r.supported_types(arch),
|
||||
Self::PowerPC(r) => r.supported_types(arch),
|
||||
Self::Hexagon(r) => r.supported_types(arch),
|
||||
Self::LoongArch(r) => r.supported_types(arch),
|
||||
Self::Mips(r) => r.supported_types(arch),
|
||||
Self::S390x(r) => r.supported_types(arch),
|
||||
Self::SpirV(r) => r.supported_types(arch),
|
||||
|
|
@ -575,6 +594,7 @@ impl InlineAsmRegClass {
|
|||
Self::PowerPC(PowerPCInlineAsmRegClass::parse(name)?)
|
||||
}
|
||||
InlineAsmArch::Hexagon => Self::Hexagon(HexagonInlineAsmRegClass::parse(name)?),
|
||||
InlineAsmArch::LoongArch64 => Self::LoongArch(LoongArchInlineAsmRegClass::parse(name)?),
|
||||
InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
|
||||
Self::Mips(MipsInlineAsmRegClass::parse(name)?)
|
||||
}
|
||||
|
|
@ -601,6 +621,7 @@ impl InlineAsmRegClass {
|
|||
Self::Nvptx(r) => r.valid_modifiers(arch),
|
||||
Self::PowerPC(r) => r.valid_modifiers(arch),
|
||||
Self::Hexagon(r) => r.valid_modifiers(arch),
|
||||
Self::LoongArch(r) => r.valid_modifiers(arch),
|
||||
Self::Mips(r) => r.valid_modifiers(arch),
|
||||
Self::S390x(r) => r.valid_modifiers(arch),
|
||||
Self::SpirV(r) => r.valid_modifiers(arch),
|
||||
|
|
@ -760,6 +781,11 @@ pub fn allocatable_registers(
|
|||
hexagon::fill_reg_map(arch, reloc_model, target_features, target, &mut map);
|
||||
map
|
||||
}
|
||||
InlineAsmArch::LoongArch64 => {
|
||||
let mut map = loongarch::regclass_map();
|
||||
loongarch::fill_reg_map(arch, reloc_model, target_features, target, &mut map);
|
||||
map
|
||||
}
|
||||
InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
|
||||
let mut map = mips::regclass_map();
|
||||
mips::fill_reg_map(arch, reloc_model, target_features, target, &mut map);
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
|
|||
- AVR
|
||||
- MSP430
|
||||
- M68k
|
||||
- LoongArch
|
||||
|
||||
## Register classes
|
||||
|
||||
|
|
@ -45,6 +46,8 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
|
|||
| M68k | `reg` | `d[0-7]`, `a[0-7]` | `r` |
|
||||
| M68k | `reg_data` | `d[0-7]` | `d` |
|
||||
| M68k | `reg_addr` | `a[0-3]` | `a` |
|
||||
| LoongArch | `reg` | `$r1`, `$r[4-20]`, `$r[23,30]` | `r` |
|
||||
| LoongArch | `freg` | `$f[0-31]` | `f` |
|
||||
|
||||
> **Notes**:
|
||||
> - NVPTX doesn't have a fixed register set, so named registers are not supported.
|
||||
|
|
@ -76,6 +79,8 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
|
|||
| MSP430 | `reg` | None | `i8`, `i16` |
|
||||
| M68k | `reg`, `reg_addr` | None | `i16`, `i32` |
|
||||
| M68k | `reg_data` | None | `i8`, `i16`, `i32` |
|
||||
| LoongArch64 | `reg` | None | `i8`, `i16`, `i32`, `i64`, `f32`, `f64` |
|
||||
| LoongArch64 | `freg` | None | `f32`, `f64` |
|
||||
|
||||
## Register aliases
|
||||
|
||||
|
|
@ -97,6 +102,10 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
|
|||
| M68k | `a5` | `bp` |
|
||||
| M68k | `a6` | `fp` |
|
||||
| M68k | `a7` | `sp`, `usp`, `ssp`, `isp` |
|
||||
| LoongArch | `$r0` | `zero` |
|
||||
| LoongArch | `$r2` | `tp` |
|
||||
| LoongArch | `$r3` | `sp` |
|
||||
| LoongArch | `$r22` | `fp` |
|
||||
|
||||
> **Notes**:
|
||||
> - TI does not mandate a frame pointer for MSP430, but toolchains are allowed
|
||||
|
|
@ -107,7 +116,7 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
|
|||
| Architecture | Unsupported register | Reason |
|
||||
| ------------ | --------------------------------------- | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
|
||||
| All | `sp` | The stack pointer must be restored to its original value at the end of an asm code block. |
|
||||
| All | `fr` (Hexagon), `$fp` (MIPS), `Y` (AVR), `r4` (MSP430), `a6` (M68k) | The frame pointer cannot be used as an input or output. |
|
||||
| All | `fr` (Hexagon), `$fp` (MIPS), `Y` (AVR), `r4` (MSP430), `a6` (M68k), `$fp` (LoongArch) | The frame pointer cannot be used as an input or output. |
|
||||
| All | `r19` (Hexagon) | This is used internally by LLVM as a "base pointer" for functions with complex stack frames. |
|
||||
| MIPS | `$0` or `$zero` | This is a constant zero register which can't be modified. |
|
||||
| MIPS | `$1` or `$at` | Reserved for assembler. |
|
||||
|
|
@ -118,6 +127,10 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
|
|||
| AVR | `r0`, `r1`, `r1r0` | Due to an issue in LLVM, the `r0` and `r1` registers cannot be used as inputs or outputs. If modified, they must be restored to their original values before the end of the block. |
|
||||
|MSP430 | `r0`, `r2`, `r3` | These are the program counter, status register, and constant generator respectively. Neither the status register nor constant generator can be written to. |
|
||||
| M68k | `a4`, `a5` | Used internally by LLVM for the base pointer and global base pointer. |
|
||||
| LoongArch | `$r0` or `$zero` | This is a constant zero register which can't be modified. |
|
||||
| LoongArch | `$r2` or `$tp` | This is reserved for TLS. |
|
||||
| LoongArch | `$r21` | This is reserved by the ABI. |
|
||||
| LoongArch | `$r31` or `$s8` | This is used internally by LLVM. |
|
||||
|
||||
## Template modifiers
|
||||
|
||||
|
|
@ -132,6 +145,8 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
|
|||
| PowerPC | `reg` | None | `0` | None |
|
||||
| PowerPC | `reg_nonzero` | None | `3` | `b` |
|
||||
| PowerPC | `freg` | None | `0` | None |
|
||||
| LoongArch | `reg` | None | `$r2` | None |
|
||||
| LoongArch | `freg` | None | `$f0` | None |
|
||||
|
||||
# Flags covered by `preserves_flags`
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,196 @@
|
|||
// min-llvm-version: 16.0
|
||||
// assembly-output: emit-asm
|
||||
// compile-flags: --target loongarch64-unknown-linux-gnu
|
||||
// needs-llvm-components: loongarch
|
||||
|
||||
#![feature(no_core, lang_items, rustc_attrs, asm_experimental_arch)]
|
||||
#![crate_type = "rlib"]
|
||||
#![no_core]
|
||||
#![allow(asm_sub_register, non_camel_case_types)]
|
||||
|
||||
#[rustc_builtin_macro]
|
||||
macro_rules! asm {
|
||||
() => {};
|
||||
}
|
||||
#[rustc_builtin_macro]
|
||||
macro_rules! concat {
|
||||
() => {};
|
||||
}
|
||||
#[rustc_builtin_macro]
|
||||
macro_rules! stringify {
|
||||
() => {};
|
||||
}
|
||||
|
||||
#[lang = "sized"]
|
||||
trait Sized {}
|
||||
#[lang = "copy"]
|
||||
trait Copy {}
|
||||
|
||||
type ptr = *const i32;
|
||||
|
||||
impl Copy for i8 {}
|
||||
impl Copy for i16 {}
|
||||
impl Copy for i32 {}
|
||||
impl Copy for i64 {}
|
||||
impl Copy for f32 {}
|
||||
impl Copy for f64 {}
|
||||
impl Copy for ptr {}
|
||||
extern "C" {
|
||||
fn extern_func();
|
||||
static extern_static: u8;
|
||||
}
|
||||
|
||||
// Hack to avoid function merging
|
||||
extern "Rust" {
|
||||
fn dont_merge(s: &str);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: sym_fn:
|
||||
// CHECK: #APP
|
||||
// CHECK: pcalau12i $t0, %got_pc_hi20(extern_func)
|
||||
// CHECK: ld.d $t0, $t0, %got_pc_lo12(extern_func)
|
||||
// CHECK: #NO_APP
|
||||
#[no_mangle]
|
||||
pub unsafe fn sym_fn() {
|
||||
asm!("la.got $r12, {}", sym extern_func);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: sym_static:
|
||||
// CHECK: #APP
|
||||
// CHECK: pcalau12i $t0, %got_pc_hi20(extern_static)
|
||||
// CHECK: ld.d $t0, $t0, %got_pc_lo12(extern_static)
|
||||
// CHECK: #NO_APP
|
||||
#[no_mangle]
|
||||
pub unsafe fn sym_static() {
|
||||
asm!("la.got $r12, {}", sym extern_static);
|
||||
}
|
||||
|
||||
macro_rules! check { ($func:ident, $ty:ty, $class:ident, $mov:literal) => {
|
||||
#[no_mangle]
|
||||
pub unsafe fn $func(x: $ty) -> $ty {
|
||||
dont_merge(stringify!($func));
|
||||
|
||||
let y;
|
||||
asm!(concat!($mov," {}, {}"), out($class) y, in($class) x);
|
||||
y
|
||||
}
|
||||
};}
|
||||
|
||||
macro_rules! check_reg { ($func:ident, $ty:ty, $reg:tt, $mov:literal) => {
|
||||
#[no_mangle]
|
||||
pub unsafe fn $func(x: $ty) -> $ty {
|
||||
dont_merge(stringify!($func));
|
||||
|
||||
let y;
|
||||
asm!(concat!($mov, " ", $reg, ", ", $reg), lateout($reg) y, in($reg) x);
|
||||
y
|
||||
}
|
||||
};}
|
||||
|
||||
// CHECK-LABEL: reg_i8:
|
||||
// CHECK: #APP
|
||||
// CHECK: move ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(reg_i8, i8, reg, "move");
|
||||
|
||||
// CHECK-LABEL: reg_i16:
|
||||
// CHECK: #APP
|
||||
// CHECK: move ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(reg_i16, i16, reg, "move");
|
||||
|
||||
// CHECK-LABEL: reg_i32:
|
||||
// CHECK: #APP
|
||||
// CHECK: move ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(reg_i32, i32, reg, "move");
|
||||
|
||||
// CHECK-LABEL: reg_f32:
|
||||
// CHECK: #APP
|
||||
// CHECK: move ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(reg_f32, f32, reg, "move");
|
||||
|
||||
// CHECK-LABEL: reg_i64:
|
||||
// CHECK: #APP
|
||||
// CHECK: move ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(reg_i64, i64, reg, "move");
|
||||
|
||||
// CHECK-LABEL: reg_f64:
|
||||
// CHECK: #APP
|
||||
// CHECK: move ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(reg_f64, f64, reg, "move");
|
||||
|
||||
// CHECK-LABEL: reg_ptr:
|
||||
// CHECK: #APP
|
||||
// CHECK: move ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(reg_ptr, ptr, reg, "move");
|
||||
|
||||
// CHECK-LABEL: freg_f32:
|
||||
// CHECK: #APP
|
||||
// CHECK: fmov.s $f{{[a-z0-9]+}}, $f{{[a-z0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(freg_f32, f32, freg, "fmov.s");
|
||||
|
||||
// CHECK-LABEL: freg_f64:
|
||||
// CHECK: #APP
|
||||
// CHECK: fmov.d $f{{[a-z0-9]+}}, $f{{[a-z0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(freg_f64, f64, freg, "fmov.d");
|
||||
|
||||
// CHECK-LABEL: r4_i8:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $a0, $a0
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(r4_i8, i8, "$r4", "move");
|
||||
|
||||
// CHECK-LABEL: r4_i16:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $a0, $a0
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(r4_i16, i16, "$r4", "move");
|
||||
|
||||
// CHECK-LABEL: r4_i32:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $a0, $a0
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(r4_i32, i32, "$r4", "move");
|
||||
|
||||
// CHECK-LABEL: r4_f32:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $a0, $a0
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(r4_f32, f32, "$r4", "move");
|
||||
|
||||
// CHECK-LABEL: r4_i64:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $a0, $a0
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(r4_i64, i64, "$r4", "move");
|
||||
|
||||
// CHECK-LABEL: r4_f64:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $a0, $a0
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(r4_f64, f64, "$r4", "move");
|
||||
|
||||
// CHECK-LABEL: r4_ptr:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $a0, $a0
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(r4_ptr, ptr, "$r4", "move");
|
||||
|
||||
// CHECK-LABEL: f0_f32:
|
||||
// CHECK: #APP
|
||||
// CHECK: fmov.s $f{{[a-z0-9]+}}, $f{{[a-z0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(f0_f32, f32, "$f0", "fmov.s");
|
||||
|
||||
// CHECK-LABEL: f0_f64:
|
||||
// CHECK: #APP
|
||||
// CHECK: fmov.d $f{{[a-z0-9]+}}, $f{{[a-z0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(f0_f64, f64, "$f0", "fmov.d");
|
||||
Loading…
Reference in New Issue