mirror of https://github.com/rust-lang/rust.git
Auto merge of #77337 - lzutao:asm-mips64, r=Amanieu
Add asm! support for mips64 - [x] Updated `src/doc/unstable-book/src/library-features/asm.md`. - [ ] No vector type support. I don't know much about those types. cc #76839
This commit is contained in:
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commit
7bc5839e99
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@ -259,7 +259,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
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InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {}
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InlineAsmArch::Nvptx64 => {}
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InlineAsmArch::Hexagon => {}
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InlineAsmArch::Mips => {}
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InlineAsmArch::Mips | InlineAsmArch::Mips64 => {}
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}
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}
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if !options.contains(InlineAsmOptions::NOMEM) {
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@ -710,6 +710,7 @@ fn llvm_fixup_input(
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// MIPS only supports register-length arithmetics.
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Primitive::Int(Integer::I8 | Integer::I16, _) => bx.zext(value, bx.cx.type_i32()),
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Primitive::F32 => bx.bitcast(value, bx.cx.type_i32()),
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Primitive::F64 => bx.bitcast(value, bx.cx.type_i64()),
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_ => value,
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},
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_ => value,
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@ -785,6 +786,7 @@ fn llvm_fixup_output(
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Primitive::Int(Integer::I8, _) => bx.trunc(value, bx.cx.type_i8()),
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Primitive::Int(Integer::I16, _) => bx.trunc(value, bx.cx.type_i16()),
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Primitive::F32 => bx.bitcast(value, bx.cx.type_f32()),
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Primitive::F64 => bx.bitcast(value, bx.cx.type_f64()),
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_ => value,
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},
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_ => value,
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@ -854,6 +856,7 @@ fn llvm_fixup_output_type(
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// MIPS only supports register-length arithmetics.
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Primitive::Int(Integer::I8 | Integer::I16, _) => cx.type_i32(),
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Primitive::F32 => cx.type_i32(),
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Primitive::F64 => cx.type_i64(),
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_ => layout.llvm_type(cx),
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},
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_ => layout.llvm_type(cx),
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@ -32,11 +32,12 @@ impl MipsInlineAsmRegClass {
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pub fn supported_types(
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self,
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_arch: InlineAsmArch,
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arch: InlineAsmArch,
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) -> &'static [(InlineAsmType, Option<&'static str>)] {
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match self {
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Self::reg => types! { _: I8, I16, I32, F32; },
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Self::freg => types! { _: F32; },
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match (self, arch) {
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(Self::reg, InlineAsmArch::Mips64) => types! { _: I8, I16, I32, I64, F32, F64; },
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(Self::reg, _) => types! { _: I8, I16, I32, F32; },
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(Self::freg, _) => types! { _: F32, F64; },
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}
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}
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}
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@ -44,31 +45,31 @@ impl MipsInlineAsmRegClass {
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// The reserved registers are somewhat taken from <https://git.io/JUR1k#L150>.
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def_regs! {
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Mips MipsInlineAsmReg MipsInlineAsmRegClass {
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v0: reg = ["$2", "$v0"],
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v1: reg = ["$3", "$v1"],
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a0: reg = ["$4", "$a0"],
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a1: reg = ["$5", "$a1"],
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a2: reg = ["$6", "$a2"],
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a3: reg = ["$7", "$a3"],
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r2: reg = ["$2"],
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r3: reg = ["$3"],
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r4: reg = ["$4"],
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r5: reg = ["$5"],
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r6: reg = ["$6"],
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r7: reg = ["$7"],
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// FIXME: Reserve $t0, $t1 if in mips16 mode.
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t0: reg = ["$8", "$t0"],
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t1: reg = ["$9", "$t1"],
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t2: reg = ["$10", "$t2"],
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t3: reg = ["$11", "$t3"],
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t4: reg = ["$12", "$t4"],
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t5: reg = ["$13", "$t5"],
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t6: reg = ["$14", "$t6"],
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t7: reg = ["$15", "$t7"],
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s0: reg = ["$16", "$s0"],
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s1: reg = ["$17", "$s1"],
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s2: reg = ["$18", "$s2"],
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s3: reg = ["$19", "$s3"],
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s4: reg = ["$20", "$s4"],
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s5: reg = ["$21", "$s5"],
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s6: reg = ["$22", "$s6"],
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s7: reg = ["$23", "$s7"],
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t8: reg = ["$24", "$t8"],
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t9: reg = ["$25", "$t9"],
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r8: reg = ["$8"],
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r9: reg = ["$9"],
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r10: reg = ["$10"],
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r11: reg = ["$11"],
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r12: reg = ["$12"],
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r13: reg = ["$13"],
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r14: reg = ["$14"],
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r15: reg = ["$15"],
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r16: reg = ["$16"],
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r17: reg = ["$17"],
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r18: reg = ["$18"],
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r19: reg = ["$19"],
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r20: reg = ["$20"],
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r21: reg = ["$21"],
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r22: reg = ["$22"],
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r23: reg = ["$23"],
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r24: reg = ["$24"],
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r25: reg = ["$25"],
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f0: freg = ["$f0"],
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f1: freg = ["$f1"],
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f2: freg = ["$f2"],
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@ -101,21 +102,21 @@ def_regs! {
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f29: freg = ["$f29"],
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f30: freg = ["$f30"],
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f31: freg = ["$f31"],
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#error = ["$0", "$zero"] =>
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#error = ["$0"] =>
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"constant zero cannot be used as an operand for inline asm",
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#error = ["$1", "$at"] =>
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#error = ["$1"] =>
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"reserved for assembler (Assembler Temp)",
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#error = ["$26", "$k0"] =>
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#error = ["$26"] =>
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"OS-reserved register cannot be used as an operand for inline asm",
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#error = ["$27", "$k1"] =>
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#error = ["$27"] =>
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"OS-reserved register cannot be used as an operand for inline asm",
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#error = ["$28", "$gp"] =>
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#error = ["$28"] =>
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"the global pointer cannot be used as an operand for inline asm",
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#error = ["$29", "$sp"] =>
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#error = ["$29"] =>
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"the stack pointer cannot be used as an operand for inline asm",
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#error = ["$30", "$s8", "$fp"] =>
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#error = ["$30"] =>
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"the frame pointer cannot be used as an operand for inline asm",
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#error = ["$31", "$ra"] =>
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#error = ["$31"] =>
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"the return address register cannot be used as an operand for inline asm",
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}
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}
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@ -176,6 +176,7 @@ pub enum InlineAsmArch {
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Nvptx64,
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Hexagon,
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Mips,
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Mips64,
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}
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impl FromStr for InlineAsmArch {
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@ -192,6 +193,7 @@ impl FromStr for InlineAsmArch {
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"nvptx64" => Ok(Self::Nvptx64),
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"hexagon" => Ok(Self::Hexagon),
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"mips" => Ok(Self::Mips),
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"mips64" => Ok(Self::Mips64),
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_ => Err(()),
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}
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}
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@ -259,7 +261,7 @@ impl InlineAsmReg {
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InlineAsmArch::Hexagon => {
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Self::Hexagon(HexagonInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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InlineAsmArch::Mips => {
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InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
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Self::Mips(MipsInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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})
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@ -409,7 +411,9 @@ impl InlineAsmRegClass {
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InlineAsmArch::Hexagon => {
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Self::Hexagon(HexagonInlineAsmRegClass::parse(arch, name)?)
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}
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InlineAsmArch::Mips => Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?),
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InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
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Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?)
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}
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})
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})
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}
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@ -565,7 +569,7 @@ pub fn allocatable_registers(
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hexagon::fill_reg_map(arch, has_feature, target, &mut map);
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map
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}
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InlineAsmArch::Mips => {
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InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
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let mut map = mips::regclass_map();
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mips::fill_reg_map(arch, has_feature, target, &mut map);
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map
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@ -27,7 +27,7 @@ Inline assembly is currently supported on the following architectures:
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- RISC-V
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- NVPTX
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- Hexagon
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- MIPS32
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- MIPS32r2 and MIPS64r2
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## Basic usage
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@ -513,8 +513,8 @@ Here is the list of currently supported register classes:
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| ARM | `qreg` | `q[0-15]` | `w` |
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| ARM | `qreg_low8` | `q[0-7]` | `t` |
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| ARM | `qreg_low4` | `q[0-3]` | `x` |
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| MIPS32 | `reg` | `$[2-25]` | `r` |
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| MIPS32 | `freg` | `$f[0-31]` | `f` |
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| MIPS | `reg` | `$[2-25]` | `r` |
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| MIPS | `freg` | `$f[0-31]` | `f` |
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| NVPTX | `reg16` | None\* | `h` |
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| NVPTX | `reg32` | None\* | `r` |
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| NVPTX | `reg64` | None\* | `l` |
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@ -551,7 +551,9 @@ Each register class has constraints on which value types they can be used with.
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| ARM | `dreg` | `vfp2` | `i64`, `f64`, `i8x8`, `i16x4`, `i32x2`, `i64x1`, `f32x2` |
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| ARM | `qreg` | `neon` | `i8x16`, `i16x8`, `i32x4`, `i64x2`, `f32x4` |
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| MIPS32 | `reg` | None | `i8`, `i16`, `i32`, `f32` |
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| MIPS32 | `freg` | None | `f32` |
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| MIPS32 | `freg` | None | `f32`, `f64` |
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| MIPS64 | `reg` | None | `i8`, `i16`, `i32`, `i64`, `f32`, `f64` |
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| MIPS64 | `freg` | None | `f32`, `f64` |
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| NVPTX | `reg16` | None | `i8`, `i16` |
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| NVPTX | `reg32` | None | `i8`, `i16`, `i32`, `f32` |
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| NVPTX | `reg64` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` |
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@ -600,7 +602,6 @@ Some registers have multiple names. These are all treated by the compiler as ide
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| ARM | `r13` | `sp` |
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| ARM | `r14` | `lr` |
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| ARM | `r15` | `pc` |
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| MIPS32 | `$[2-25]` | Please [see the Wikipedia page][mips-regs] |
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| RISC-V | `x0` | `zero` |
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| RISC-V | `x1` | `ra` |
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| RISC-V | `x2` | `sp` |
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@ -621,8 +622,6 @@ Some registers have multiple names. These are all treated by the compiler as ide
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| Hexagon | `r30` | `fr` |
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| Hexagon | `r31` | `lr` |
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[mips-regs]: https://en.wikibooks.org/wiki/MIPS_Assembly/Register_File#Registers
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Some registers cannot be used for input or output operands:
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| Architecture | Unsupported register | Reason |
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@ -637,11 +636,11 @@ Some registers cannot be used for input or output operands:
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| x86 | `st([0-7])` | x87 registers are not currently supported (but may be in the future). |
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| AArch64 | `xzr` | This is a constant zero register which can't be modified. |
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| ARM | `pc` | This is the program counter, not a real register. |
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| MIPS32 | `$0` or `$zero` | This is a constant zero register which can't be modified. |
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| MIPS32 | `$1` or `$at` | Reserved for assembler. |
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| MIPS32 | `$26`/`$k0`, `$27`/`$k1` | OS-reserved registers. |
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| MIPS32 | `$28`/`$gp` | Global pointer cannot be used as inputs or outputs. |
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| MIPS32 | `$ra` | Return address cannot be used as inputs or outputs. |
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| MIPS | `$0` or `$zero` | This is a constant zero register which can't be modified. |
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| MIPS | `$1` or `$at` | Reserved for assembler. |
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| MIPS | `$26`/`$k0`, `$27`/`$k1` | OS-reserved registers. |
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| MIPS | `$28`/`$gp` | Global pointer cannot be used as inputs or outputs. |
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| MIPS | `$ra` | Return address cannot be used as inputs or outputs. |
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| RISC-V | `x0` | This is a constant zero register which can't be modified. |
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| RISC-V | `gp`, `tp` | These registers are reserved and cannot be used as inputs or outputs. |
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| Hexagon | `lr` | This is the link register which cannot be used as an input or output. |
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@ -689,8 +688,8 @@ The supported modifiers are a subset of LLVM's (and GCC's) [asm template argumen
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| ARM | `dreg` | None | `d0` | `P` |
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| ARM | `qreg` | None | `q0` | `q` |
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| ARM | `qreg` | `e` / `f` | `d0` / `d1` | `e` / `f` |
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| MIPS32 | `reg` | None | `$2` | None |
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| MIPS32 | `freg` | None | `$f0` | None |
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| MIPS | `reg` | None | `$2` | None |
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| MIPS | `freg` | None | `$f0` | None |
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| NVPTX | `reg16` | None | `rs0` | None |
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| NVPTX | `reg32` | None | `r0` | None |
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| NVPTX | `reg64` | None | `rd0` | None |
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@ -1,6 +1,8 @@
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// no-system-llvm
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// revisions: mips32 mips64
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// assembly-output: emit-asm
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// compile-flags: --target mips-unknown-linux-gnu
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//[mips32] compile-flags: --target mips-unknown-linux-gnu
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//[mips64] compile-flags: --target mips64-unknown-linux-gnuabi64
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// needs-llvm-components: mips
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#![feature(no_core, lang_items, rustc_attrs, repr_simd)]
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@ -32,7 +34,9 @@ impl Copy for i8 {}
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impl Copy for u8 {}
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impl Copy for i16 {}
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impl Copy for i32 {}
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impl Copy for i64 {}
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impl Copy for f32 {}
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impl Copy for f64 {}
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impl Copy for ptr {}
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extern "C" {
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fn extern_func();
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@ -44,148 +48,190 @@ extern "Rust" {
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fn dont_merge(s: &str);
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}
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macro_rules! check { ($func:ident, $ty:ty, $class:ident) => {
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macro_rules! check { ($func:ident, $ty:ty, $class:ident, $mov:literal) => {
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#[no_mangle]
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pub unsafe fn $func(x: $ty) -> $ty {
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dont_merge(stringify!($func));
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let y;
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asm!("move {}, {}", out($class) y, in($class) x);
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asm!(concat!($mov," {}, {}"), out($class) y, in($class) x);
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y
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}
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};}
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macro_rules! check_reg { ($func:ident, $ty:ty, $reg:tt) => {
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macro_rules! check_reg { ($func:ident, $ty:ty, $reg:tt, $mov:literal) => {
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#[no_mangle]
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pub unsafe fn $func(x: $ty) -> $ty {
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dont_merge(stringify!($func));
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let y;
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asm!(concat!("move ", $reg, ", ", $reg), lateout($reg) y, in($reg) x);
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asm!(concat!($mov, " ", $reg, ", ", $reg), lateout($reg) y, in($reg) x);
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y
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}
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};}
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// CHECK-LABEL: sym_static:
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// CHECK: #APP
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// CHECK: lw $3, %got(extern_static)
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// CHECK: #NO_APP
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// mips32-LABEL: sym_static_32:
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// mips32: #APP
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// mips32: lw $3, %got(extern_static)
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// mips32: #NO_APP
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#[cfg(mips32)]
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#[no_mangle]
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pub unsafe fn sym_static() {
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dont_merge(stringify!($func));
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asm!("la $v1, {}", sym extern_static);
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pub unsafe fn sym_static_32() {
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asm!("lw $v1, {}", sym extern_static);
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}
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// CHECK-LABEL: sym_fn:
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// CHECK: #APP
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// CHECK: lw $3, %got(extern_func)
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// CHECK: #NO_APP
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// mips32-LABEL: sym_fn_32:
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// mips32: #APP
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// mips32: lw $3, %got(extern_func)
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// mips32: #NO_APP
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#[cfg(mips32)]
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#[no_mangle]
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pub unsafe fn sym_fn() {
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dont_merge(stringify!($func));
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pub unsafe fn sym_fn_32() {
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asm!("lw $v1, {}", sym extern_func);
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}
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asm!("la $v1, {}", sym extern_func);
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// mips64-LABEL: sym_static_64:
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// mips64: #APP
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// mips64: ld $3, %got_disp(extern_static)
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// mips64: #NO_APP
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#[cfg(mips64)]
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#[no_mangle]
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pub unsafe fn sym_static_64() {
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asm!("ld $v1, {}", sym extern_static);
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}
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||||
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// mips64-LABEL: sym_fn_64:
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// mips64: #APP
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// mips64: ld $3, %got_disp(extern_func)
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// mips64: #NO_APP
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#[cfg(mips64)]
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#[no_mangle]
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pub unsafe fn sym_fn_64() {
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asm!("ld $v1, {}", sym extern_func);
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}
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||||
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||||
// CHECK-LABEL: reg_f32:
|
||||
// CHECK: #APP
|
||||
// CHECK: mov.s $f{{[0-9]+}}, $f{{[0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
#[no_mangle]
|
||||
pub unsafe fn reg_f32(x: f32) -> f32 {
|
||||
dont_merge("reg_f32");
|
||||
let y;
|
||||
asm!("mov.s {}, {}", out(freg) y, in(freg) x);
|
||||
y
|
||||
}
|
||||
check!(reg_f32, f32, freg, "mov.s");
|
||||
|
||||
// CHECK-LABEL: f0_f32:
|
||||
// CHECK: #APP
|
||||
// CHECK: mov.s $f0, $f0
|
||||
// CHECK: #NO_APP
|
||||
#[no_mangle]
|
||||
pub unsafe fn f0_f32(x: f32) -> f32 {
|
||||
dont_merge("f0_f32");
|
||||
let y;
|
||||
asm!("mov.s $f0, $f0", lateout("$f0") y, in("$f0") x);
|
||||
y
|
||||
}
|
||||
check_reg!(f0_f32, f32, "$f0", "mov.s");
|
||||
|
||||
// CHECK-LABEL: reg_f32_64:
|
||||
// CHECK: #APP
|
||||
// CHECK: mov.d $f{{[0-9]+}}, $f{{[0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(reg_f32_64, f32, freg, "mov.d");
|
||||
|
||||
// CHECK-LABEL: f0_f32_64:
|
||||
// CHECK: #APP
|
||||
// CHECK: mov.d $f0, $f0
|
||||
// CHECK: #NO_APP
|
||||
#[no_mangle]
|
||||
check_reg!(f0_f32_64, f32, "$f0", "mov.d");
|
||||
|
||||
// CHECK-LABEL: reg_f64:
|
||||
// CHECK: #APP
|
||||
// CHECK: mov.d $f{{[0-9]+}}, $f{{[0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
#[no_mangle]
|
||||
check!(reg_f64, f64, freg, "mov.d");
|
||||
|
||||
// CHECK-LABEL: f0_f64:
|
||||
// CHECK: #APP
|
||||
// CHECK: mov.d $f0, $f0
|
||||
// CHECK: #NO_APP
|
||||
#[no_mangle]
|
||||
check_reg!(f0_f64, f64, "$f0", "mov.d");
|
||||
|
||||
// CHECK-LABEL: reg_ptr:
|
||||
// CHECK: #APP
|
||||
// CHECK: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(reg_ptr, ptr, reg);
|
||||
check!(reg_ptr, ptr, reg, "move");
|
||||
|
||||
// CHECK-LABEL: reg_i32:
|
||||
// CHECK: #APP
|
||||
// CHECK: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(reg_i32, i32, reg);
|
||||
check!(reg_i32, i32, reg, "move");
|
||||
|
||||
// CHECK-LABEL: reg_f32_soft:
|
||||
// CHECK: #APP
|
||||
// CHECK: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(reg_f32_soft, f32, reg);
|
||||
check!(reg_f32_soft, f32, reg, "move");
|
||||
|
||||
// mips64-LABEL: reg_f64_soft:
|
||||
// mips64: #APP
|
||||
// mips64: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
// mips64: #NO_APP
|
||||
#[cfg(mips64)]
|
||||
check!(reg_f64_soft, f64, reg, "move");
|
||||
|
||||
// CHECK-LABEL: reg_i8:
|
||||
// CHECK: #APP
|
||||
// CHECK: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(reg_i8, i8, reg);
|
||||
check!(reg_i8, i8, reg, "move");
|
||||
|
||||
// CHECK-LABEL: reg_u8:
|
||||
// CHECK: #APP
|
||||
// CHECK: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(reg_u8, u8, reg);
|
||||
check!(reg_u8, u8, reg, "move");
|
||||
|
||||
// CHECK-LABEL: reg_i16:
|
||||
// CHECK: #APP
|
||||
// CHECK: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(reg_i16, i16, reg);
|
||||
check!(reg_i16, i16, reg, "move");
|
||||
|
||||
// CHECK-LABEL: t0_ptr:
|
||||
// mips64-LABEL: reg_i64:
|
||||
// mips64: #APP
|
||||
// mips64: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
// mips64: #NO_APP
|
||||
#[cfg(mips64)]
|
||||
check!(reg_i64, i64, reg, "move");
|
||||
|
||||
// CHECK-LABEL: r8_ptr:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $8, $8
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(t0_ptr, ptr, "$t0");
|
||||
check_reg!(r8_ptr, ptr, "$8", "move");
|
||||
|
||||
// CHECK-LABEL: t0_i32:
|
||||
// CHECK-LABEL: r8_i32:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $8, $8
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(t0_i32, i32, "$t0");
|
||||
check_reg!(r8_i32, i32, "$8", "move");
|
||||
|
||||
// CHECK-LABEL: t0_f32:
|
||||
// CHECK-LABEL: r8_f32:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $8, $8
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(t0_f32, f32, "$t0");
|
||||
check_reg!(r8_f32, f32, "$8", "move");
|
||||
|
||||
// CHECK-LABEL: t0_i8:
|
||||
// CHECK-LABEL: r8_i8:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $8, $8
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(t0_i8, i8, "$t0");
|
||||
check_reg!(r8_i8, i8, "$8", "move");
|
||||
|
||||
// CHECK-LABEL: t0_u8:
|
||||
// CHECK-LABEL: r8_u8:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $8, $8
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(t0_u8, u8, "$t0");
|
||||
|
||||
// CHECK-LABEL: t0_i16:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $8, $8
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(t0_i16, i16, "$t0");
|
||||
check_reg!(r8_u8, u8, "$8", "move");
|
||||
|
||||
// CHECK-LABEL: r8_i16:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $8, $8
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(r8_i16, i16, "$8");
|
||||
check_reg!(r8_i16, i16, "$8", "move");
|
||||
|
|
|
|||
Loading…
Reference in New Issue