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Rollup merge of #94339 - Amanieu:arm-d32, r=nagisa 

ARM: Only allow using d16-d31 with asm! when supported by the target

Support can be determined by checking for the "d32" LLVM feature.

r? ```````````````@nagisa```````````````
This commit is contained in:
Dylan DPC 2022-03-04 02:06:40 +01:00 committed by GitHub
parent cdfb39ef07 7cee1b4aeb
commit 79c71d1f9e
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3 changed files with 6 additions and 1 deletions
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1
compiler/rustc_codegen_ssa/src/target_features.rs
View File

@ -39,6 +39,7 @@ const ARM_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
// #[target_feature].
("thumb-mode", Some(sym::arm_target_feature)),
("thumb2", Some(sym::arm_target_feature)),
("d32", Some(sym::arm_target_feature)),
];
const AARCH64_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[

1
compiler/rustc_span/src/symbol.rs
View File

@ -539,6 +539,7 @@ symbols! {
custom_inner_attributes,
custom_test_frameworks,
d,
d32,
dbg_macro,
dead_code,
dealloc,

5
compiler/rustc_target/src/asm/arm.rs
View File

@ -50,9 +50,12 @@ impl ArmInlineAsmRegClass {
match self {
Self::reg => types! { _: I8, I16, I32, F32; },
Self::sreg | Self::sreg_low16 => types! { vfp2: I32, F32; },
Self::dreg | Self::dreg_low16 | Self::dreg_low8 => types! {
Self::dreg_low16 | Self::dreg_low8 => types! {
vfp2: I64, F64, VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF32(2);
},
Self::dreg => types! {
d32: I64, F64, VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF32(2);
},
Self::qreg | Self::qreg_low8 | Self::qreg_low4 => types! {
neon: VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4);
},