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Use 16bit simd indices

This commit is contained in:
bjorn3 2020-03-27 16:42:28 +01:00
parent d2c5b4be68
commit 33fd4c47aa
2 changed files with 18 additions and 18 deletions
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30
src/intrinsics/mod.rs
View File

@ -141,10 +141,10 @@ macro atomic_minmax($fx:expr, $cc:expr, <$T:ident> ($ptr:ident, $src:ident) -> $
fn lane_type_and_count<'tcx>(
tcx: TyCtxt<'tcx>,
layout: TyLayout<'tcx>,
) -> (TyLayout<'tcx>, u32) {
) -> (TyLayout<'tcx>, u16) {
assert!(layout.ty.is_simd());
let lane_count = match layout.fields {
layout::FieldPlacement::Array { stride: _, count } => u32::try_from(count).unwrap(),
layout::FieldPlacement::Array { stride: _, count } => u16::try_from(count).unwrap(),
_ => unreachable!("lane_type_and_count({:?})", layout),
};
let lane_layout = layout.field(&ty::layout::LayoutCx {
@ -264,19 +264,19 @@ macro simd_cmp {
$ret.write_cvalue($fx, CValue::by_val(val, $ret.layout()));
} else {
simd_pair_for_each_lane(
$fx,
$x,
$y,
$ret,
|fx, lane_layout, res_lane_layout, x_lane, y_lane| {
let res_lane = match lane_layout.ty.kind {
ty::Uint(_) | ty::Int(_) => codegen_icmp(fx, IntCC::$cc, x_lane, y_lane),
_ => unreachable!("{:?}", lane_layout.ty),
};
bool_to_zero_or_max_uint(fx, res_lane_layout, res_lane)
},
);
simd_pair_for_each_lane(
$fx,
$x,
$y,
$ret,
|fx, lane_layout, res_lane_layout, x_lane, y_lane| {
let res_lane = match lane_layout.ty.kind {
ty::Uint(_) | ty::Int(_) => codegen_icmp(fx, IntCC::$cc, x_lane, y_lane),
_ => unreachable!("{:?}", lane_layout.ty),
};
bool_to_zero_or_max_uint(fx, res_lane_layout, res_lane)
},
);
}
},
($fx:expr, $cc_u:ident|$cc_s:ident($x:ident, $y:ident) -> $ret:ident) => {

6
src/intrinsics/simd.rs
View File

@ -53,7 +53,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
// simd_shuffle32<T, U>(x: T, y: T, idx: [u32; 32]) -> U
_ if intrinsic.starts_with("simd_shuffle"), (c x, c y, o idx) {
let n: u32 = intrinsic["simd_shuffle".len()..].parse().unwrap();
let n: u16 = intrinsic["simd_shuffle".len()..].parse().unwrap();
assert_eq!(x.layout(), y.layout());
let layout = x.layout();
@ -85,8 +85,8 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
fx.tcx.data_layout.endian,
&idx_bytes[4*i.. 4*i + 4],
).expect("read_target_uint");
u32::try_from(idx).expect("try_from u32")
}).collect::<Vec<u32>>()
u16::try_from(idx).expect("try_from u32")
}).collect::<Vec<u16>>()
};
for &idx in &indexes {