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Implement all x86 vendor intrinsics used by glam
Fixes rust-lang/rustc_codegen_cranelift#1463
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@ -170,6 +170,65 @@ pub(crate) fn codegen_x86_llvm_intrinsic_call<'tcx>(
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}
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}
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"llvm.x86.sse.add.ss" => {
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// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_add_ss&ig_expand=171
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intrinsic_args!(fx, args => (a, b); intrinsic);
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assert_eq!(a.layout(), b.layout());
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assert_eq!(a.layout(), ret.layout());
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let layout = a.layout();
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let (_, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
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assert!(lane_ty.is_floating_point());
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let ret_lane_layout = fx.layout_of(lane_ty);
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ret.write_cvalue(fx, a);
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let a_lane = a.value_lane(fx, 0).load_scalar(fx);
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let b_lane = b.value_lane(fx, 0).load_scalar(fx);
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let res = fx.bcx.ins().fadd(a_lane, b_lane);
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let res_lane = CValue::by_val(res, ret_lane_layout);
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ret.place_lane(fx, 0).write_cvalue(fx, res_lane);
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}
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"llvm.x86.sse.sqrt.ps" => {
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// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sqrt_ps&ig_expand=6245
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intrinsic_args!(fx, args => (a); intrinsic);
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// FIXME use vector instructions when possible
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simd_for_each_lane(fx, a, ret, &|fx, _lane_ty, _res_lane_ty, lane| {
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fx.bcx.ins().sqrt(lane)
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});
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}
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"llvm.x86.sse.max.ps" => {
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// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_max_ps&ig_expand=4357
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intrinsic_args!(fx, args => (a, b); intrinsic);
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simd_pair_for_each_lane(
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fx,
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a,
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b,
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ret,
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&|fx, _lane_ty, _res_lane_ty, a_lane, b_lane| fx.bcx.ins().fmax(a_lane, b_lane),
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);
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}
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"llvm.x86.sse.min.ps" => {
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// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_min_ps&ig_expand=4489
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intrinsic_args!(fx, args => (a, b); intrinsic);
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simd_pair_for_each_lane(
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fx,
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a,
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b,
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ret,
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&|fx, _lane_ty, _res_lane_ty, a_lane, b_lane| fx.bcx.ins().fmin(a_lane, b_lane),
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);
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}
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"llvm.x86.sse.cmp.ps" | "llvm.x86.sse2.cmp.pd" => {
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let (x, y, kind) = match args {
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[x, y, kind] => (x, y, kind),
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