Add some register aliases + documentation, and correct a bound
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@ -4,7 +4,7 @@ module Rex
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module Arch
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#
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# Everything here is mostly stolen from vlad's perl x86 stuff
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# Everything here is mostly stolen from vlad's perl sparc stuff
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#
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module Sparc
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@ -21,10 +21,11 @@ module Sparc
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'l4' => 20, 'l5' => 21, 'l6' => 22, 'l7' => 23,
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'i0' => 24, 'i1' => 25, 'i2' => 26, 'i3' => 27,
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'i4' => 28, 'i5' => 29, 'i6' => 30, 'i7' => 31,
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'sp' => 14, 'fp' => 30,
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} # :nodoc:
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#
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# TODO: documentation required.
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# Encodes a SETHI instruction with the value 'constant' being put into 'dst' register
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#
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def self.sethi(constant, dst)
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[
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@ -35,7 +36,7 @@ module Sparc
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end
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#
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# TODO: documentation required.
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# Encodes an OR instruction with the value 'constant' being OR'ed with the 'src' register into the 'dst' register
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#
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def self.ori(src, constant, dst)
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[
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@ -49,10 +50,11 @@ module Sparc
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end
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#
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# TODO: documentation required.
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# Puts 'constant' into the 'dst' register using as few instructions as possible by checking the size of the value.
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# XXX: signedness support
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#
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def self.set(constant, dst)
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if (constant <= 4096 and constant >= 0)
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if (constant <= 4095 and constant >= 0)
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ori('g0', constant, dst)
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elsif (constant & 0x3ff)
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set_dword(constant, dst)
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@ -61,6 +63,9 @@ module Sparc
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end
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end
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#
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# Puts 'constant' into the 'dst' register using both sethi and ori (necessary to use both uncessarily in some cases with encoders)
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#
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#
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# TODO: documentation required.
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#
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