227 lines
7.5 KiB
Plaintext
227 lines
7.5 KiB
Plaintext
/***************************************************************************************************
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* Copyright (c) 2017 - 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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**************************************************************************************************/
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/*! \file
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\brief Unit test for the OrderedSequenceBarrier class
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*/
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#include "../common/cutlass_unit_test.h"
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#include <thrust/host_vector.h>
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#include <thrust/device_vector.h>
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#include <cute/tensor.hpp>
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#include <cute/arch/cluster_sm90.hpp>
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#include <cutlass/util/reference/host/gemm.h>
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#include <cutlass/cluster_launch.hpp>
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#include "cutlass/core_io.h"
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#include "cutlass/util/print_error.hpp"
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#include "cutlass/util/GPU_Clock.hpp"
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#include "testbed.h"
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#include "cutlass/pipeline/pipeline.hpp"
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#include "cutlass/arch/barrier.h"
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#include "cute/arch/cluster_sm90.hpp"
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using namespace cute;
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//////////////////// KERNEL /////////////////////////
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template<typename OrderedSequencer>
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struct SharedStorage
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{
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typename OrderedSequencer::SharedStorage storage;
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};
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// Goal of this kernel is to complete deadlock-free
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template<int Stages, int GroupCount, int ThreadsPerGroup>
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__global__ static
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void ordered_sequence_device(uint32_t const num_iterations)
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{
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extern __shared__ char shared_memory[];
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using SequenceBarrier = typename cutlass::OrderedSequenceBarrier<Stages, GroupCount>;
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using SmemStorage = SharedStorage<SequenceBarrier>;
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SmemStorage& shared_storage = *reinterpret_cast<SmemStorage*>(shared_memory);
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int group_idx = threadIdx.x / ThreadsPerGroup;
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typename SequenceBarrier::Params params;
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params.group_id = group_idx; // sequence ID
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params.group_size = ThreadsPerGroup; // Number of threads / participants in a group
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SequenceBarrier barrier(shared_storage.storage, params);
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// Ensure All CTAs in Cluster have completed init before issuing commits
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__syncthreads();
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cute::cluster_arrive_relaxed();
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cute::cluster_wait();
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CUTLASS_PRAGMA_NO_UNROLL
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for (int i = 0; i < num_iterations; ++i){
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barrier.wait();
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// STAGE 1 CODE...
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#ifndef NDEBUG
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int thread_idx_in_group = threadIdx.x % ThreadsPerGroup;
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if (thread_idx_in_group == 0) {
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printf("STAGE 0 : Group_IDX : %d, id = %d, iter = %d, tidx = %d\n", group_idx, params.group_id, i, threadIdx.x);
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}
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#endif
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// Simulates long running stage
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 700)
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__nanosleep(100000);
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#endif
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barrier.arrive();
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barrier.wait();
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// STAGE 2 CODE...
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#ifndef NDEBUG
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if (thread_idx_in_group == 0) {
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printf("STAGE 1 : Group_IDX : %d, id = %d, iter = %d, tidx = %d\n", group_idx, params.group_id, i, threadIdx.x);
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}
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#endif
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// Simulates long running stage
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 700)
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__nanosleep(100000);
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#endif
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barrier.arrive();
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}
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// To make sure remote SMEM doesn't get destroyed
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cute::cluster_arrive();
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cute::cluster_wait();
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}
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/////////////////////////////////////////////////////
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template<uint32_t Stages_, uint32_t GroupCount_>
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struct PipelineTest {
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//
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// Data members
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//
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static constexpr uint32_t ThreadsPerGroup = 128;
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static constexpr uint32_t BlockSize = GroupCount_ * ThreadsPerGroup;
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static constexpr uint32_t Stages = Stages_;
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static constexpr uint32_t GroupCount = GroupCount_;
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using SequenceBarrier = typename cutlass::OrderedSequenceBarrier<Stages, GroupCount>;
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using SmemStorage = SharedStorage<SequenceBarrier>;
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//
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// Methods
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//
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// Run CuTe GEMM kernel
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cudaError_t run(uint32_t const kNumIters,
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cudaStream_t stream = nullptr) {
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// Pipeline (multistage pipeline)
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auto cluster_shape = Shape<_1, _1, _1>{};
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//
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// Configure and launch
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//
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int iterations = 1;
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cudaError_t result;
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for (int iter = 0; iter < iterations; ++iter) {
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int smem_size = int(sizeof(SmemStorage));
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result = cudaFuncSetAttribute(
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ordered_sequence_device<Stages, GroupCount, ThreadsPerGroup>,
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cudaFuncAttributeMaxDynamicSharedMemorySize,
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smem_size);
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// Launch a single Cluster, with 128 thread per CTA
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dim3 dimCluster(size<0>(cluster_shape), size<1>(cluster_shape), size<2>(cluster_shape));
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dim3 dimGrid(size<0>(cluster_shape), size<1>(cluster_shape), 1);
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dim3 dimBlock(BlockSize,1,1);
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const void* kernel = (const void*)ordered_sequence_device<Stages, GroupCount, ThreadsPerGroup>;
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int iters = kNumIters;
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void* kernel_params[] = {reinterpret_cast<void*>(&iters)};
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cutlass::ClusterLauncher::launch(dimGrid, dimCluster, dimBlock, smem_size, stream, kernel, kernel_params);
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} // profiling loop ends
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result = cudaDeviceSynchronize();
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if (result != cudaSuccess) {
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std::cerr << "Error: cudaDeviceSynchronize() failed" << std::endl;
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return result;
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}
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return cudaSuccess;
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}
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};
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#if CUDA_12_0_SM90_FEATURES_SUPPORTED
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TEST(SM90_Verify_OrderedSequence, Depth_2_Length_2) {
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Options options;
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static constexpr uint32_t GroupCount = 2;
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static constexpr uint32_t Stages = 2;
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using Test = PipelineTest<Stages, GroupCount>;
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Testbed<Test> testbed(options);
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EXPECT_TRUE(testbed.verification());
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}
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TEST(SM90_Verify_OrderedSequence, Depth_2_Length_3) {
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Options options;
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static constexpr uint32_t GroupCount = 3;
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static constexpr uint32_t Stages = 2;
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using Test = PipelineTest<Stages, GroupCount>;
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Testbed<Test> testbed(options);
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EXPECT_TRUE(testbed.verification());
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}
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TEST(SM90_Verify_OrderedSequence, Depth_2_Length_4) {
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Options options;
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static constexpr uint32_t GroupCount = 4;
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static constexpr uint32_t Stages = 2;
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using Test = PipelineTest<Stages, GroupCount>;
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Testbed<Test> testbed(options);
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EXPECT_TRUE(testbed.verification());
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}
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TEST(SM90_Verify_OrderedSequence, Depth_2_Length_5) {
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Options options;
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static constexpr uint32_t GroupCount = 5;
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static constexpr uint32_t Stages = 2;
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using Test = PipelineTest<Stages, GroupCount>;
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Testbed<Test> testbed(options);
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EXPECT_TRUE(testbed.verification());
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}
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#endif
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