162 lines
3.7 KiB
Verilog
162 lines
3.7 KiB
Verilog
`timescale 1ns / 1ps
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/////////////////////////////////////////////////////////
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//module Uart_Tx_Control(CLK, Rstn,Rstn_release,Tx_Out_En,Tx_Out_Done,Tx_Out_Data,Tx_Data_Pin_A, Tx_Data_Pin_B);
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module Uart_Tx_Control(CLK, Rstn,Rstn_release,Tx_Out_En,Tx_Out_Data);
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input CLK;
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input Rstn;
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input[7:0] Rstn_release;
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input Tx_Out_En;
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// output Tx_Out_Done;
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input[7:0]Tx_Out_Data;
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// output Tx_Data_Pin_A;
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// output Tx_Data_Pin_B;
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wire Tx_Out_Done;
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wire Tx_Data_Pin_A;
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wire Tx_Data_Pin_B;
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////////////////////////////////////////////
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parameter
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State_Tx_Await =8'b0000_0000,
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State_Tx_Bit_Data =8'b0000_0001,
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State_Tx_Bit_Check =8'b0000_0011,
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State_Tx_Bit_Empty =8'b0000_0010,
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State_Tx_Bit_Done =8'b0000_0110;
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//------------------------------------------//
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reg[10:0] Tx_Data_Buffer =11'b00000000000;
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reg[7:0] Tx_State =State_Tx_Await;
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reg Tx_Data_Pin_reg =1'b1;
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reg Tx_Clk_Start =1'b0;
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reg Tx_Out_Done_reg =1'b0;
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//-------------------------------------------//
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reg[7:0] Tx_Bit_Cnt =8'd0;
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reg[15:0] Tx_Clk_Cnt =16'd0;
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reg Tx_Check_Bit =1'b0;
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//----------------------------------------//
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always @ (posedge CLK or negedge Rstn)
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if(!Rstn)
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begin
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Tx_State<=State_Tx_Await;
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Tx_Data_Buffer<=11'b00000000000;
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Tx_Clk_Start<=1'b0;
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Tx_Data_Pin_reg<=1'b1;
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Tx_Out_Done_reg<=1'b0;
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end
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else if (Rstn_release==8'h11)
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begin
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case (Tx_State)
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State_Tx_Await:
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if(Tx_Out_En==1'b1) // high active
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begin
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Tx_State<=State_Tx_Bit_Data;
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Tx_Clk_Start<=1'b1;
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Tx_Data_Pin_reg<=1'b0;//
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Tx_Data_Buffer[0]<=1'b0;
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Tx_Data_Buffer[8:1]<=Tx_Out_Data[7:0];
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Tx_Data_Buffer[10]<=1'b1;
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Tx_Out_Done_reg<=1'b0;
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end
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else
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begin
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Tx_State<=State_Tx_Await;
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Tx_Clk_Start<=1'b0;
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Tx_Data_Pin_reg<=1'b1;//
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end
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State_Tx_Bit_Data://
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if(Tx_Bit_Cnt>=8'd8 && Tx_Clk_Cnt>=16'd521)
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begin
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Tx_State<=State_Tx_Bit_Check;
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Tx_Data_Buffer[9]<=Tx_Check_Bit^1'b1;
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end
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else
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Tx_Data_Pin_reg<=Tx_Data_Buffer[Tx_Bit_Cnt];//
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State_Tx_Bit_Check://
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if(Tx_Bit_Cnt>=8'd10 && Tx_Clk_Cnt>=16'd521)
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begin
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Tx_State<=State_Tx_Bit_Empty;
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Tx_Data_Pin_reg<=1'b1;
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end
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// else if(Tx_Bit_Cnt>=8'd11)
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// begin
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// Tx_State<=State_Tx_Bit_Done;
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// Tx_Data_Pin_reg<=1'b1;
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// end
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else
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Tx_Data_Pin_reg<=Tx_Data_Buffer[Tx_Bit_Cnt];
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State_Tx_Bit_Empty://
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if(Tx_Bit_Cnt>=8'd13)//
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begin
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Tx_State<=State_Tx_Bit_Done;
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Tx_Clk_Start<=1'b0;
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Tx_Out_Done_reg<=1'b1;
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Tx_Clk_Start<=1'b1;
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end
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else
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Tx_State<=State_Tx_Bit_Empty;
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State_Tx_Bit_Done:
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if(Tx_Out_En==1'b0)
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begin
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Tx_State<=State_Tx_Await;
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Tx_Out_Done_reg<=1'b0;
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end
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else
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Tx_State<=State_Tx_Bit_Done;
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default:
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Tx_State<=State_Tx_Await;
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endcase
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end
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//-------------------------------------------------------------//
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always @ (posedge CLK or negedge Rstn)
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if(!Rstn)
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begin
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Tx_Bit_Cnt<=8'd0;
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Tx_Clk_Cnt<=16'd0;
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Tx_Check_Bit<=1'b0;
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end
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else if (Rstn_release==8'h11)
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begin
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if(Tx_Clk_Start)
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if(Tx_Bit_Cnt>=13)
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Tx_Bit_Cnt<=8'd0;
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else if (Tx_Clk_Cnt>=16'd521)//521 for 60Mhz Osci,138 for 16MHz
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begin
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Tx_Bit_Cnt<=Tx_Bit_Cnt+1'b1;
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Tx_Clk_Cnt<=16'd0;
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if(Tx_Bit_Cnt<8'd9)
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Tx_Check_Bit<=Tx_Check_Bit^Tx_Data_Buffer[Tx_Bit_Cnt+1];
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end
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else
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Tx_Clk_Cnt<=Tx_Clk_Cnt+1'b1;
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else
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begin
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Tx_Bit_Cnt<=8'd0;
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Tx_Clk_Cnt<=16'd0;
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Tx_Check_Bit<=1'b0;
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end
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end
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//----------------------------------------//
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assign Tx_Data_Pin_A=Tx_Data_Pin_reg;
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assign Tx_Data_Pin_B=Tx_Data_Pin_reg;
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assign Tx_Out_Done=Tx_Out_Done_reg;
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endmodule
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