`timescale 1ns / 1ps
/////////////////////////////////////////////////////////
//module Uart_Tx_Control(CLK, Rstn,Rstn_release,Tx_Out_En,Tx_Out_Done,Tx_Out_Data,Tx_Data_Pin_A, Tx_Data_Pin_B);
   
module Uart_Tx_Control(CLK, Rstn,Rstn_release,Tx_Out_En,Tx_Out_Data);
   
    input CLK;
    input Rstn;
	 input[7:0]	Rstn_release;
	 
	 input  Tx_Out_En;
	// output Tx_Out_Done;
	 input[7:0]Tx_Out_Data;
  //  output Tx_Data_Pin_A;
	// output Tx_Data_Pin_B;



wire Tx_Out_Done;
wire Tx_Data_Pin_A;
wire Tx_Data_Pin_B;
////////////////////////////////////////////
parameter 
		State_Tx_Await			=8'b0000_0000,
		State_Tx_Bit_Data    =8'b0000_0001,
		State_Tx_Bit_Check	=8'b0000_0011,
		State_Tx_Bit_Empty	=8'b0000_0010,
		State_Tx_Bit_Done		=8'b0000_0110;

//------------------------------------------//	
reg[10:0] Tx_Data_Buffer	   =11'b00000000000;
reg[7:0]  Tx_State				=State_Tx_Await;
reg Tx_Data_Pin_reg			   =1'b1;
reg Tx_Clk_Start				   =1'b0;
reg Tx_Out_Done_reg			   =1'b0;
//-------------------------------------------//	
reg[7:0]  Tx_Bit_Cnt			      =8'd0;
reg[15:0] Tx_Clk_Cnt			      =16'd0;
reg       Tx_Check_Bit				=1'b0;
//----------------------------------------//	


always @ (posedge CLK or negedge Rstn)
	if(!Rstn)
		begin
			Tx_State<=State_Tx_Await;
			Tx_Data_Buffer<=11'b00000000000;
			Tx_Clk_Start<=1'b0;
			Tx_Data_Pin_reg<=1'b1;
			Tx_Out_Done_reg<=1'b0;
		end

	else if (Rstn_release==8'h11) 
	 begin
		case (Tx_State)
			State_Tx_Await:
					if(Tx_Out_En==1'b1)  // high active
						begin
							Tx_State<=State_Tx_Bit_Data;
							Tx_Clk_Start<=1'b1;
							Tx_Data_Pin_reg<=1'b0;//
							Tx_Data_Buffer[0]<=1'b0;
							Tx_Data_Buffer[8:1]<=Tx_Out_Data[7:0];
							Tx_Data_Buffer[10]<=1'b1;
							Tx_Out_Done_reg<=1'b0;
					
						end
					else
						begin
							Tx_State<=State_Tx_Await;
							Tx_Clk_Start<=1'b0;
							Tx_Data_Pin_reg<=1'b1;//
						end
			
			State_Tx_Bit_Data://
				if(Tx_Bit_Cnt>=8'd8 && Tx_Clk_Cnt>=16'd521)
					begin
						Tx_State<=State_Tx_Bit_Check;		
						Tx_Data_Buffer[9]<=Tx_Check_Bit^1'b1;
					end
				else
					Tx_Data_Pin_reg<=Tx_Data_Buffer[Tx_Bit_Cnt];//
						
			State_Tx_Bit_Check://
				if(Tx_Bit_Cnt>=8'd10 && Tx_Clk_Cnt>=16'd521)	
					begin	
						Tx_State<=State_Tx_Bit_Empty;
						Tx_Data_Pin_reg<=1'b1;	
					end
//				else if(Tx_Bit_Cnt>=8'd11)
//					begin	
//						Tx_State<=State_Tx_Bit_Done;
//						Tx_Data_Pin_reg<=1'b1;					
//					end					
				else
					Tx_Data_Pin_reg<=Tx_Data_Buffer[Tx_Bit_Cnt];
					
					
			State_Tx_Bit_Empty://
				if(Tx_Bit_Cnt>=8'd13)//
					begin
						Tx_State<=State_Tx_Bit_Done;
						Tx_Clk_Start<=1'b0;
						Tx_Out_Done_reg<=1'b1;
						Tx_Clk_Start<=1'b1;
					end
				else
					Tx_State<=State_Tx_Bit_Empty;

			State_Tx_Bit_Done:
				if(Tx_Out_En==1'b0)
					begin
						Tx_State<=State_Tx_Await;
						Tx_Out_Done_reg<=1'b0;
					end
				else
					Tx_State<=State_Tx_Bit_Done;
			default:
					Tx_State<=State_Tx_Await;
      endcase	
   end		
//-------------------------------------------------------------//
		
				


always @ (posedge CLK or negedge Rstn)
	if(!Rstn)
		begin
			Tx_Bit_Cnt<=8'd0;
			Tx_Clk_Cnt<=16'd0;
			Tx_Check_Bit<=1'b0;
		end

	else if (Rstn_release==8'h11) 
   begin	
	if(Tx_Clk_Start)
		if(Tx_Bit_Cnt>=13)
			Tx_Bit_Cnt<=8'd0;
		else if (Tx_Clk_Cnt>=16'd521)//521 for 60Mhz Osci,138 for 16MHz 
			begin
				Tx_Bit_Cnt<=Tx_Bit_Cnt+1'b1;
				Tx_Clk_Cnt<=16'd0;
				if(Tx_Bit_Cnt<8'd9)
					Tx_Check_Bit<=Tx_Check_Bit^Tx_Data_Buffer[Tx_Bit_Cnt+1];
			end
	   else
			Tx_Clk_Cnt<=Tx_Clk_Cnt+1'b1;
	else
		begin
			Tx_Bit_Cnt<=8'd0;
			Tx_Clk_Cnt<=16'd0;
			Tx_Check_Bit<=1'b0;
		end	
   end		
//----------------------------------------//		

assign Tx_Data_Pin_A=Tx_Data_Pin_reg;
assign Tx_Data_Pin_B=Tx_Data_Pin_reg;
assign Tx_Out_Done=Tx_Out_Done_reg;
endmodule