diff --git a/src/cst/module_declaration.rs b/src/cst/module_declaration.rs index 70c9e4a..47a96ad 100644 --- a/src/cst/module_declaration.rs +++ b/src/cst/module_declaration.rs @@ -188,22 +188,15 @@ impl ModuleDeclaration { Tag::PORT_DECLARATION_LIST, Tag::PORT_DECLARATION, ]; - let mut flag = 2001; - let mut json_io_ports = Tools::match_tags(vec![json], base_path_2001.to_vec()); - if json_io_ports.len() == 0 { - // error!("FIXME: implement get_port_info_2005() here"); - // panic!("Verilog-2005 not yet supported"); - json_io_ports = Tools::match_tags(vec![json], base_path_2005.to_vec()); - flag = 2005; - } - if flag == 2001 { - println!("the version is verilog-2001"); - Self::get_port_info_2001(json_io_ports) - } else - { - println!("the version is verilog-2005"); - Self::get_port_info_2005(json_io_ports) + let json_io_ports_2001 = Tools::match_tags(vec![json], base_path_2001.to_vec()); + if json_io_ports_2001.len() == 0 { + let json_io_ports_2005 = Tools::match_tags(vec![json], base_path_2005.to_vec()); + info!("version: Verilog-2005"); + Self::get_port_info_2005(json_io_ports_2005) + } else { + info!("version: Verilog-2001"); + Self::get_port_info_2001(json_io_ports_2001) } } @@ -290,31 +283,11 @@ impl ModuleDeclaration { fn get_port_info_2005( json_io_ports: Vec<&JsonValue>, ) -> (Vec<(String, usize)>, Vec<(String, usize)>) { - let name_paths = [ - vec![ - Tag::PORT_DECLARATION, - // Tag::IDENTIFIER_LIST, - // Tag::IDENTIFIER_UNPACKED_DIMENSIONS, - Tag::UNQUALIFIED_ID, - Tag::SYMBOL_IDENTIFIER, - ], - // vec![ - // Tag::PORT_DECLARATION, - // // Tag::UNQUALIFIED_ID, - // Tag::SYMBOL_IDENTIFIER, - // ], - // vec![ - // Tag::PORT_DECLARATION, - // Tag::UNQUALIFIED_ID, - // Tag::SYMBOL_IDENTIFIER, - // ], - // vec![ - // Tag::PORT_DECLARATION, - // Tag::PORT_IDENTIFIER_LIST, - // Tag::PORT_IDENTIFIER, - // Tag::SYMBOL_IDENTIFIER, - // ], - ]; + let name_paths = [vec![ + Tag::PORT_DECLARATION, + Tag::UNQUALIFIED_ID, + Tag::SYMBOL_IDENTIFIER, + ]]; let dim_path = [ Tag::PORT_DECLARATION, @@ -365,7 +338,7 @@ impl ModuleDeclaration { get_port_info(json_output_ports), ) } - + fn get_reg_info(json: &JsonValue) -> Vec<(String, usize)> { let base_path = [ Tag::MODULE_DECLARATION, diff --git a/src/cst/tags.rs b/src/cst/tags.rs index 2e87d76..4a6e450 100644 --- a/src/cst/tags.rs +++ b/src/cst/tags.rs @@ -7,10 +7,10 @@ impl Tag { pub const MODULE_ITEM_LIST: &'static str = "kModuleItemList"; pub const MODULE_PORT_DECLARATION: &'static str = "kModulePortDeclaration"; - pub const PORT_IDENTIFIER_LIST: &'static str = "kPortIdentifierList"; - pub const PORT_IDENTIFIER: &'static str = "kPortIdentifier"; pub const PORT_DECLARATION_LIST: &'static str = "kPortDeclarationList"; pub const PORT_DECLARATION: &'static str = "kPortDeclaration"; + pub const PORT_IDENTIFIER_LIST: &'static str = "kPortIdentifierList"; + pub const PORT_IDENTIFIER: &'static str = "kPortIdentifier"; pub const IDENTIFIER_LIST: &'static str = "kIdentifierList"; pub const IDENTIFIER_UNPACKED_DIMENSIONS_LIST: &'static str = "kIdentifierUnpackedDimensionsList";