From 9d38eecf2d344349be25b1fb8eb91b2b229685fb Mon Sep 17 00:00:00 2001 From: Yanting Zhang Date: Thu, 5 May 2022 17:43:22 +0800 Subject: [PATCH] Update module_declaration.rs --- src/cst/module_declaration.rs | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/cst/module_declaration.rs b/src/cst/module_declaration.rs index 920fb56..873a43f 100644 --- a/src/cst/module_declaration.rs +++ b/src/cst/module_declaration.rs @@ -24,7 +24,7 @@ impl ModuleDeclaration { SymbolDeclaration::declare_param(json, &mut context); Self::gen_entity_data(json, &mut context); - Self::set_port_names(&mut context); + Self::set_port_names(json, &mut context); Self::init_regs_and_wires(&mut context); Self::gen_assignment(json, &mut context); @@ -87,7 +87,7 @@ impl ModuleDeclaration { .new_data(UnitKind::Entity, entity_name, entity_signature); } - fn set_port_names(context: &mut ModuleContext) { + fn set_port_names<'a>(json: &'a JsonValue, context: &mut ModuleContext<'a>) { let mut builder = UnitContext::builder(&mut context.unit_ctx.data); for (raw_name, &arg) in &context.unit_ctx.raw_name_to_arg { @@ -97,6 +97,7 @@ impl ModuleDeclaration { .unit_ctx .raw_name_to_value .insert(raw_name.clone(), arg_value); + context.syntax_table.insert_value(builder.unit(), arg_value, json); trace!("found I/O port {}", raw_name); } }