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cst-to-llhd
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Update module_declaration.rs

This commit is contained in:
Yanting Zhang 2022-05-05 17:43:22 +08:00
parent 2b6bb64539
commit 9d38eecf2d
1 changed files with 3 additions and 2 deletions
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5
src/cst/module_declaration.rs
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@ -24,7 +24,7 @@ impl ModuleDeclaration {
SymbolDeclaration::declare_param(json, &mut context);
Self::gen_entity_data(json, &mut context);
Self::set_port_names(&mut context);
Self::set_port_names(json, &mut context);
Self::init_regs_and_wires(&mut context);
Self::gen_assignment(json, &mut context);
@ -87,7 +87,7 @@ impl ModuleDeclaration {
.new_data(UnitKind::Entity, entity_name, entity_signature);
}
fn set_port_names(context: &mut ModuleContext) {
fn set_port_names<'a>(json: &'a JsonValue, context: &mut ModuleContext<'a>) {
let mut builder = UnitContext::builder(&mut context.unit_ctx.data);
for (raw_name, &arg) in &context.unit_ctx.raw_name_to_arg {
@ -97,6 +97,7 @@ impl ModuleDeclaration {
.unit_ctx
.raw_name_to_value
.insert(raw_name.clone(), arg_value);
context.syntax_table.insert_value(builder.unit(), arg_value, json);
trace!("found I/O port {}", raw_name);
}
}