From 92c19776cc3af8a6f50b5c9ca974b05e9da73419 Mon Sep 17 00:00:00 2001 From: Guojie Luo Date: Mon, 14 Feb 2022 22:00:45 +0800 Subject: [PATCH] Add one more test case --- src/cst/module_declaration.rs | 31 +- src/main.rs | 13 +- test/export-json.sh | 21 + test/uart-tx/Uart_Tx_Control.v | 161 + test/uart-tx/uart-tx.json | 8595 ++++++++++++++++++++++++++++++++ 5 files changed, 8805 insertions(+), 16 deletions(-) create mode 100755 test/export-json.sh create mode 100644 test/uart-tx/Uart_Tx_Control.v create mode 100644 test/uart-tx/uart-tx.json diff --git a/src/cst/module_declaration.rs b/src/cst/module_declaration.rs index 825c72c..cd18171 100644 --- a/src/cst/module_declaration.rs +++ b/src/cst/module_declaration.rs @@ -34,8 +34,8 @@ impl ModuleDeclaration { ], ); - let input_info = &Self::get_tagged_info(json_ports, Tag::INPUT); - let output_info = &Self::get_tagged_info(json_ports, Tag::OUTPUT); + let input_info = &Self::get_port_info(json_ports, Tag::INPUT); + let output_info = &Self::get_port_info(json_ports, Tag::OUTPUT); let mut arg_table = HashMap::new(); for (name, width) in input_info { @@ -148,20 +148,23 @@ impl ModuleDeclaration { .map(|x| x["text"].to_string()) .collect(); - let num_ports = raw_vec_dims.len() / 2; - let vec_dims: Vec<(String, String)> = raw_vec_dims - .iter() - .step_by(2) - .into_iter() - .zip(raw_vec_dims[1..].iter().step_by(2).into_iter()) - .map(|(x, y)| (x.to_string(), y.to_string())) - .collect(); - assert_eq!(vec_dims.len(), num_ports); + let num_vec_ports = raw_vec_dims.len() / 2; + let vec_dims = match num_vec_ports { + 0 => Vec::new(), + _ => raw_vec_dims + .iter() + .step_by(2) + .into_iter() + .zip(raw_vec_dims[1..].iter().step_by(2).into_iter()) + .map(|(x, y)| (x.to_string(), y.to_string())) + .collect::>(), + }; + assert_eq!(vec_dims.len(), num_vec_ports); vec_dims } - fn get_tagged_info(json_ports: &Vec<&JsonValue>, tag: &str) -> Vec<(String, usize)> { + fn get_port_info(json_ports: &Vec<&JsonValue>, tag: &str) -> Vec<(String, usize)> { let json_tagged_ports = &json_ports .iter() .filter(|&x| x["children"].members().filter(|&x| x["tag"] == tag).count() > 0) @@ -172,7 +175,7 @@ impl ModuleDeclaration { let vec_names = &Self::get_vec_names(json_tagged_ports); let vec_dims = &Self::get_vec_dims(json_tagged_ports); - let tagged_info = [ + let port_info = [ bit_names .iter() .map(|x| (x.to_string(), 1)) @@ -189,6 +192,6 @@ impl ModuleDeclaration { ] .concat(); - tagged_info + port_info } } diff --git a/src/main.rs b/src/main.rs index 84026c2..6637b30 100644 --- a/src/main.rs +++ b/src/main.rs @@ -46,8 +46,17 @@ fn main_inner() -> Result<(), String> { let module_list = cst::DescriptionList::codegen(json_tree); for module in module_list { - println!("{}===", module.dump()); - println!(""); + println!("{}", module.dump()); + + for entity in module.entities() { + println!( + r#"entity "{}" has {} input ports and {} output ports"#, + entity.name(), + entity.input_args().count(), + entity.output_args().count() + ); + println!(""); + } } Ok(()) diff --git a/test/export-json.sh b/test/export-json.sh new file mode 100755 index 0000000..62fa498 --- /dev/null +++ b/test/export-json.sh @@ -0,0 +1,21 @@ +#!/bin/bash + +verilog=$1 + +usage=$(cat << EOF +Usage: ./export_json.sh + +Dependencies: +* include the path to "verible-verilog-syntax" in PATH + * download [verible](https://github.com/chipsalliance/verible/releases) +* install "jq" using a package manager from your OS + * or skip the last command in the pipe +EOF +) + +if [[ -f $verilog ]] ; then + verible-verilog-syntax --printtree --export_json $verilog | tr -d ' \t\n' | sed "s/,null//g" | sed "s/null,//g" | jq +else + echo "$usage" + echo "" +fi diff --git a/test/uart-tx/Uart_Tx_Control.v b/test/uart-tx/Uart_Tx_Control.v new file mode 100644 index 0000000..ce496c1 --- /dev/null +++ b/test/uart-tx/Uart_Tx_Control.v @@ -0,0 +1,161 @@ +`timescale 1ns / 1ps +///////////////////////////////////////////////////////// +//module Uart_Tx_Control(CLK, Rstn,Rstn_release,Tx_Out_En,Tx_Out_Done,Tx_Out_Data,Tx_Data_Pin_A, Tx_Data_Pin_B); + +module Uart_Tx_Control(CLK, Rstn,Rstn_release,Tx_Out_En,Tx_Out_Data); + + input CLK; + input Rstn; + input[7:0] Rstn_release; + + input Tx_Out_En; + // output Tx_Out_Done; + input[7:0]Tx_Out_Data; + // output Tx_Data_Pin_A; + // output Tx_Data_Pin_B; + + + +wire Tx_Out_Done; +wire Tx_Data_Pin_A; +wire Tx_Data_Pin_B; +//////////////////////////////////////////// +parameter + State_Tx_Await =8'b0000_0000, + State_Tx_Bit_Data =8'b0000_0001, + State_Tx_Bit_Check =8'b0000_0011, + State_Tx_Bit_Empty =8'b0000_0010, + State_Tx_Bit_Done =8'b0000_0110; + +//------------------------------------------// +reg[10:0] Tx_Data_Buffer =11'b00000000000; +reg[7:0] Tx_State =State_Tx_Await; +reg Tx_Data_Pin_reg =1'b1; +reg Tx_Clk_Start =1'b0; +reg Tx_Out_Done_reg =1'b0; +//-------------------------------------------// +reg[7:0] Tx_Bit_Cnt =8'd0; +reg[15:0] Tx_Clk_Cnt =16'd0; +reg Tx_Check_Bit =1'b0; +//----------------------------------------// + + +always @ (posedge CLK or negedge Rstn) + if(!Rstn) + begin + Tx_State<=State_Tx_Await; + Tx_Data_Buffer<=11'b00000000000; + Tx_Clk_Start<=1'b0; + Tx_Data_Pin_reg<=1'b1; + Tx_Out_Done_reg<=1'b0; + end + + else if (Rstn_release==8'h11) + begin + case (Tx_State) + State_Tx_Await: + if(Tx_Out_En==1'b1) // high active + begin + Tx_State<=State_Tx_Bit_Data; + Tx_Clk_Start<=1'b1; + Tx_Data_Pin_reg<=1'b0;// + Tx_Data_Buffer[0]<=1'b0; + Tx_Data_Buffer[8:1]<=Tx_Out_Data[7:0]; + Tx_Data_Buffer[10]<=1'b1; + Tx_Out_Done_reg<=1'b0; + + end + else + begin + Tx_State<=State_Tx_Await; + Tx_Clk_Start<=1'b0; + Tx_Data_Pin_reg<=1'b1;// + end + + State_Tx_Bit_Data:// + if(Tx_Bit_Cnt>=8'd8 && Tx_Clk_Cnt>=16'd521) + begin + Tx_State<=State_Tx_Bit_Check; + Tx_Data_Buffer[9]<=Tx_Check_Bit^1'b1; + end + else + Tx_Data_Pin_reg<=Tx_Data_Buffer[Tx_Bit_Cnt];// + + State_Tx_Bit_Check:// + if(Tx_Bit_Cnt>=8'd10 && Tx_Clk_Cnt>=16'd521) + begin + Tx_State<=State_Tx_Bit_Empty; + Tx_Data_Pin_reg<=1'b1; + end +// else if(Tx_Bit_Cnt>=8'd11) +// begin +// Tx_State<=State_Tx_Bit_Done; +// Tx_Data_Pin_reg<=1'b1; +// end + else + Tx_Data_Pin_reg<=Tx_Data_Buffer[Tx_Bit_Cnt]; + + + State_Tx_Bit_Empty:// + if(Tx_Bit_Cnt>=8'd13)// + begin + Tx_State<=State_Tx_Bit_Done; + Tx_Clk_Start<=1'b0; + Tx_Out_Done_reg<=1'b1; + Tx_Clk_Start<=1'b1; + end + else + Tx_State<=State_Tx_Bit_Empty; + + State_Tx_Bit_Done: + if(Tx_Out_En==1'b0) + begin + Tx_State<=State_Tx_Await; + Tx_Out_Done_reg<=1'b0; + end + else + Tx_State<=State_Tx_Bit_Done; + default: + Tx_State<=State_Tx_Await; + endcase + end +//-------------------------------------------------------------// + + + + +always @ (posedge CLK or negedge Rstn) + if(!Rstn) + begin + Tx_Bit_Cnt<=8'd0; + Tx_Clk_Cnt<=16'd0; + Tx_Check_Bit<=1'b0; + end + + else if (Rstn_release==8'h11) + begin + if(Tx_Clk_Start) + if(Tx_Bit_Cnt>=13) + Tx_Bit_Cnt<=8'd0; + else if (Tx_Clk_Cnt>=16'd521)//521 for 60Mhz Osci,138 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