25 lines
667 B
Systemverilog
25 lines
667 B
Systemverilog
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// see https://www.geeksforgeeks.org/counter-design-using-verilog-hdl/
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// Here we will learn to write a verilog HDL to design a 4 bit counter
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module counter(
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input clk,
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input reset,
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input up_down,
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input load,
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input [3:0] data,
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output [3:0] count);
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reg [3:0] count;
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//always block will be executed at each and every positive edge of the clock
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always@(posedge clk)
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begin
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if(reset) //Set Counter to Zero
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count <= 0;
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else if(load) //load the counter with data value
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count <= data;
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else if(up_down) //count up
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count <= count + 1;
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else //count down
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count <= count - 1;
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end
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endmodule :counter
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