124 lines
4.7 KiB
Python
124 lines
4.7 KiB
Python
import sys
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sys.path.append("../..")
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import util
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'''
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class Params():
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def __init__(self, typ, name, value, optional = False):
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self.type = typ
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self.name = name
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self.range = []
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self.value = value
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self.optional = optional
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def check_valid(self):
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return True
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'''
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class GenusSynth():
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def __init__(self, design):
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self.params = dict()
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self.params["effort"] = "medium"
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self.params["is_incremental"] = True
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self.params["spatial"] = False
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self.design = design
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#self.design.obj_hdl = design.obj_path + "/" + design.top_name + ".vh"
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#self.design.obj_sdc = design.obj_path + "/" + design.top_name + "_synth.sdc"
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#self.design.rpt_gates = design.rpt_path + "/" + "gates_synth.rpt"
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#self.design.rpt_timing = design.rpt_path + "/" + "timing_synth.rpt"
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#self.design.rpt_power = design.rpt_path + "/" + "power_synth.rpt"
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def getObjHDL(self):
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obj_path = util.getObjPath(self.design, "Cadence")
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obj_hdl = obj_path + "/" + self.design.top_name + ".vh"
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return obj_hdl
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def getObjSDC(self):
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obj_path = util.getObjPath(self.design, "Cadence")
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obj_sdc = obj_path + "/" + self.design.top_name + ".sdc"
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return obj_sdc
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def getRptGates(self):
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rpt_path = util.getRptPath(self.design, "Cadence")
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rpt_gates = rpt_path + "/" + "gates_synth.rpt"
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return rpt_gates
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def getRptTiming(self):
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rpt_path = util.getRptPath(self.design, "Cadence")
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rpt_timing = rpt_path + "/" + "timing_synth.rpt"
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return rpt_timing
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def getRptPower(self):
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rpt_path = util.getRptPath(self.design, "Cadence")
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rpt_power = rpt_path + "/" + "gates_synth.rpt"
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return rpt_power
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def setParams(self, param, optional):
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if self.params.get(param) is not None:
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self.params[param] = optional
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else:
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assert False, 'Unknown param'
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def config(self, design, tcl_file):
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rtl_file = util.getHDL(self.design)
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lib_file = util.getLib(self.design)
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hdl_path = util.getHDLPath(self.design, "Cadence")
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lib_path = util.getLibPath(self.design, "Cadence")
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#tcl = open(tcl_file + ".tcl", 'w', encoding='utf-8')
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tcl_path = util.getScriptPath(self.design, "Cadence")
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tcl = open(tcl_path + "/" + tcl_file + ".tcl", 'w', encoding='utf-8')
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#tcl.write('set hdl_files %s\n'%(self.design.rtl_file))
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tcl.write('set hdl_files {%s}\n'%(rtl_file))
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tcl.write('set DESIGN %s\n'%(self.design.top_name))
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tcl.write('set clkpin %s\n'%(self.design.clk_name))
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tcl.write('set delay %d\n'%(self.design.delay))
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#tcl.write('set_attribute hdl_search_path %s\n'%(self.design.hdl_path))
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#tcl.write('set_attribute lib_search_path %s\n'%(self.design.lib_path))
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tcl.write('set_attribute hdl_search_path %s\n'%(hdl_path))
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tcl.write('set_attribute lib_search_path %s\n'%(lib_path))
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tcl.write('set_attribute information_level 6 \n')
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tcl.write('set_attribute library %s\n'%(lib_file))
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tcl.write('read_hdl ${hdl_files} \n')
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tcl.write('elaborate $DESIGN \n')
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tcl.write('set clock [define_clock -period ${delay} -name ${clkpin} [clock_ports]]\n')
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tcl.write('external_delay -input 0 -clock clk [find / -port ports_in/*]\n')
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tcl.write('external_delay -output 0 -clock clk [find / -port ports_out/*]\n')
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tcl.write('dc::set_clock_transition .4 clk\n')
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tcl.write('check_design -unresolved\n')
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tcl.write('report timing -lint\n')
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ret = 'synthesize -to_mapped'
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for i in self.params:
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if self.params[i]:
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ret = ret + " -" + i
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tcl.write(ret + '\n')
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#tcl.write("report timing > %s\n"%(self.design.rpt_timing))
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#tcl.write('report gates > %s\n'%(self.design.rpt_gates))
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#tcl.write('report power > %s\n'%(self.design.rpt_power))
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#tcl.write('write_hdl -mapped > %s\n'%(self.design.obj_hdl))
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#tcl.write('write_sdc > %s\n'%(self.design.obj_sdc))
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tcl.write("report timing > %s\n"%(self.getRptTiming()))
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tcl.write('report gates > %s\n'%(self.getRptGates()))
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tcl.write('report power > %s\n'%(self.getRptPower()))
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tcl.write('write_hdl -mapped > %s\n'%(self.getObjHDL()))
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tcl.write('write_sdc > %s\n'%(self.getObjSDC()))
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tcl.close()
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'''
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class Output(object):
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def __init__(self, design):
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pass
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def config(self, file_name):
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f = open(file_name + ".tcl", "w")
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# to-do
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f.close()
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'''
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