33 lines
1.0 KiB
Python
33 lines
1.0 KiB
Python
import time
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import os
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import subprocess
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class Design(object):
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def __init__(self):
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self.top_name = "design" + time.strftime("%Y-%m-%d", time.localtime())
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self.is_Chisel_design = False
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self.rtl_input = " "
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self.Chisel_input = " "
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self.result_dir = "./design/"
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self.lib_name = "gscl45nm"
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self.lef_input = " "
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self.liberty_input = " "
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self.clk_name = "clk"
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self.delay = 100
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def Chisel2RTL(self, verbose):
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"""
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Compile Chisel design to single verilog file
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"""
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print("========== Compiling Chisel to Verilog... ==========")
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chisel_dir = self.Chisel_input
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output = "" if verbose else f" > {os.path.join(self.result_dir, self.top_name, self.lib_name, 'reports/', 'sbt.log')}"
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cmd = f'sbt "runMain {self.top_name}"' + output
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subprocess.run(cmd, cwd=chisel_dir, shell=True)
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self.rtl_input = os.path.join(self.Chisel_input, 'generated', '%s.v'%self.top_name)
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