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@ -1,15 +1,3 @@
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*.pyc
|
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.DS_Store
|
||||
__pycache__/
|
||||
results/
|
||||
demo/alu-chisel/generated/
|
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demo/alu-chisel/target/
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demo/alu-chisel/project/target/streams/
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gurobi.log
|
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*.ini
|
||||
!config.sample.ini
|
||||
!config.sample1.ini
|
||||
!config.sample2.ini
|
||||
!config.sample3.ini
|
||||
|
||||
|
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design/*/scripts/
|
||||
|
|
|
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|
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@ -1,6 +0,0 @@
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|||
[submodule "thirdparty/DREAMPlace"]
|
||||
path = thirdparty/DREAMPlace
|
||||
url = https://github.com/limbo018/DREAMPlace
|
||||
[submodule "thirdparty/yosys"]
|
||||
path = thirdparty/yosys
|
||||
url = https://github.com/YosysHQ/yosys
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
BSD 3-Clause License
|
||||
|
||||
Copyright (c) 2019-2020, Peking University
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
* Neither the name of the copyright holder nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
129
README.md
129
README.md
|
|
@ -1,129 +1,8 @@
|
|||
# Cocoon: An Infrastructure for Integrated EDA
|
||||
Cocoon is an open-source infrastructure for integrated EDA with interoperability and interactivity. It contains a set of cross-tool interfaces and plays the role of EDA agent that can help IC designers choose EDA point tools to assemble a legal design flow and to produce ICs with a higher quality of results (QoR). It can also help EDA researchers and tool developer research new design methodology and cross-stage optimization. Below are key features of Cocoon:
|
||||
- Agile RTL-to-GDSII frontend and backend VLSI flow generation.
|
||||
- Completely user-defined tech library, component EDA tool and design constraints.
|
||||
- Multi-flow parallelism and automatic iterative circuit timing optimization.
|
||||
Cocoon is an open source infrastructure for integrated EDA with interoperability and interactivity.
|
||||
It contains a set of cross-tool interfaces and plays the role of EDA agent that can help IC designers
|
||||
choose EDA point tools to assemble a legal design flow and to produce ICs with higher quality of results (QoR).
|
||||
It can also help EDA researchers and tool developer do research on new design methodology and cross-stage optimization.
|
||||
|
||||
## Cocoon Architecture
|
||||
|
||||
|
||||
## Dependency
|
||||
- Python3
|
||||
- Genus or [Yosys](https://github.com/YosysHQ/yosys)
|
||||
- Innovus
|
||||
- [DREAMPlace](https://github.com/limbo018/DREAMPlace) (optional)
|
||||
- JDK 8+ and sbt (optional)
|
||||
|
||||
## Setup
|
||||
- Clone this repo:
|
||||
```shell
|
||||
git clone https://github.com/pku-dasys/cocoon.git
|
||||
```
|
||||
- If you are going to use DREAMPlace and yosys in your flow, pull git submodules in the root directory. Then solve their own dependencies.
|
||||
```shell
|
||||
git submodule init
|
||||
git submodule update
|
||||
```
|
||||
Or alternatively, pull all the submodules when cloning the repo.
|
||||
```shell
|
||||
git clone --recursive https://github.com/pku-dasys/cocoon.git
|
||||
```
|
||||
- Build DREAMPlace (optional):
|
||||
```shell
|
||||
cd ./thirdparty/DREAMPlace/
|
||||
mkdir build
|
||||
cd build/
|
||||
cmake .. -DCMAKE_INSTALL_PREFIX=../install
|
||||
make
|
||||
make install
|
||||
```
|
||||
- Build yosys (optional):
|
||||
```shell
|
||||
cd ./thirdparty/yosys/
|
||||
mkdir build
|
||||
cd build/
|
||||
make -f ../Makefile
|
||||
```
|
||||
|
||||
## Basic Usage
|
||||
Once you have installed the previous required dependencies, you can run Cocoon from the command line using your customized configuration file in INI format.
|
||||
|
||||
Three demo configurations `demo/config.sample1.ini`, `demo/config.sample2.ini`, `demo/config.sample3.ini` are provided, where your can find detailed description of user-defined options from the comments. Here's an example of 2 parallel flows.
|
||||
```ini
|
||||
[gcd]
|
||||
# Design settings
|
||||
design_name = gcd
|
||||
is_Chisel_design = False
|
||||
rtl_input = ./gcd/gcd.v
|
||||
Chisel_input =
|
||||
result_dir = ../results/
|
||||
clk_name = clk
|
||||
delay = 1000
|
||||
|
||||
# Library settings
|
||||
lib_name = gscl45nm
|
||||
lef_input = ./lib/gscl45nm.lef
|
||||
liberty_input = ./lib/gscl45nm.lib
|
||||
|
||||
# Flow settings
|
||||
flow = {'synth':'yosys', 'placement':'dreamplace', 'routing':'innovus'}
|
||||
n_iter_IFT = 0
|
||||
verbose = False
|
||||
cadence_version = 19
|
||||
|
||||
|
||||
[ALU(Chisel)]
|
||||
# Design settings
|
||||
design_name = AluTop
|
||||
is_Chisel_design = True
|
||||
rtl_input =
|
||||
Chisel_input = ./alu-chisel/
|
||||
result_dir = ../results/
|
||||
clk_name = clk
|
||||
delay = 1000
|
||||
|
||||
# Library settings
|
||||
lib_name = gscl45nm
|
||||
lef_input = ./lib/gscl45nm.lef
|
||||
liberty_input = ./lib/gscl45nm.lib
|
||||
|
||||
# Flow settings
|
||||
flow = {'synth':'genus', 'placement':'innovus', 'routing':'innovus'}
|
||||
n_iter_IFT = 0
|
||||
verbose = False
|
||||
cadence_version = 19
|
||||
```
|
||||
You can directly run with the sample configurations with the demo designs, gcd (Verilog) and ALU (Chisel), together with the open-source FreePDK45nm library we provide in `./demo/`. For example:
|
||||
```bash
|
||||
cd cocoon/
|
||||
python run.py ./demo/config.sample1.ini
|
||||
```
|
||||
With correctly customized configuration, you can run your own flow by executing:
|
||||
```bash
|
||||
cd cocoon/
|
||||
python run.py /Path/to/your/config.ini
|
||||
```
|
||||
## Ongoing work
|
||||
- Integrate more EDA tools
|
||||
- Efficient resource scheduling
|
||||
- Legality check (LVS, DRC, etc.) and post-simulation (e.g. timing, power)
|
||||
- Support design-space search and optimization
|
||||
|
||||
## Related works
|
||||
- Berkeley [Hammer](https://github.com/ucb-bar/hammer/)
|
||||
- Stanford [mflowgen](https://github.com/mflowgen/mflowgen)
|
||||
- [SiliconCompiler](https://github.com/siliconcompiler/siliconcompiler)
|
||||
- [qflow](https://github.com/RTimothyEdwards/qflow)
|
||||
|
||||
## Publication
|
||||
|
||||
If you use cocoon in your research, please cite our WOSET'20 paper: ``Jiaxi Zhang, Tuo Dai, Zhengzheng Ma, Yibo Lin, Guojie Luo, "Cocoon: An Open Source Infrastructure for Integrated EDA with Interoperability and Interactivity", Workshop on Open-Source EDA Technology (WOSET), November 2020.``
|
||||
```
|
||||
@article{zhang-cocoon-woset2020,
|
||||
title = "{Cocoon: An Open Source Infrastructure for Integrated EDA with Interoperability and Interactivity}",
|
||||
author = {Jiaxi Zhang and Tuo Dai and Zhengzheng Ma and Yibo Lin and Guojie Luo}
|
||||
journal = {Workshop on Open-Source EDA Technology (WOSET)},
|
||||
month = {Nov},
|
||||
year = {2020},
|
||||
}
|
||||
```
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
import os
|
||||
import sys
|
||||
sys.path.append("../..")
|
||||
import util
|
||||
|
||||
class InnovusCTS(object):
|
||||
|
|
@ -24,7 +25,7 @@ class InnovusCTS(object):
|
|||
self.params[param] = True
|
||||
|
||||
def config(self, design, tcl_file):
|
||||
tcl_path = util.getScriptPath(self.design)
|
||||
tcl_path = util.getScriptPath(self.design, "Cadence")
|
||||
ret = 'ccopt_design'
|
||||
if self.outDir != '!':
|
||||
ret = ret + ' -outDir ' + self.outDir
|
||||
|
|
@ -34,8 +35,7 @@ class InnovusCTS(object):
|
|||
if self.params[i] == True:
|
||||
ret = ret + ' -' + i
|
||||
|
||||
tcl = open(os.path.join(tcl_path, tcl_file + ".tcl"), 'w', encoding='utf-8')
|
||||
tcl.write('set_ccopt_property buffer_cells "CLKBUF1 CLKBUF2 CLKBUF3"\n')
|
||||
tcl = open(tcl_path + "/" + tcl_file + ".tcl", 'w', encoding='utf-8')
|
||||
tcl.writelines(ret)
|
||||
tcl.close()
|
||||
return ret
|
||||
return ret
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
import os
|
||||
import sys
|
||||
sys.path.append("../..")
|
||||
import util
|
||||
|
||||
class InnovusDRC():
|
||||
|
|
@ -16,9 +17,9 @@ class InnovusDRC():
|
|||
assert False, 'Unknown param'
|
||||
|
||||
def config(self, design, tcl_file):
|
||||
tcl_path = util.getScriptPath(self.design)
|
||||
tcl_path = util.getScriptPath(self.design, "Cadence")
|
||||
ret = 'check_design'
|
||||
if self.params['out_file'] != 'default':
|
||||
if self.params['out_file'] is not 'default':
|
||||
ret = ret + " -out_file " + self.params['out_file']
|
||||
|
||||
if self.params['no_check']:
|
||||
|
|
@ -26,7 +27,7 @@ class InnovusDRC():
|
|||
else:
|
||||
ret = ret + " -type " + self.params['type']
|
||||
|
||||
tcl = open(os.path.join(tcl_path, tcl_file + ".tcl"), 'w', encoding='utf-8')
|
||||
tcl = open(tcl_path + "/" + tcl_file + ".tcl", 'w', encoding='utf-8')
|
||||
tcl.writelines(ret)
|
||||
tcl.close()
|
||||
|
||||
|
|
@ -1,13 +1,11 @@
|
|||
import os
|
||||
import sys
|
||||
sys.path.append("../..")
|
||||
import util
|
||||
|
||||
class InnovusFloorplan():
|
||||
def __init__(self, design):
|
||||
self.params = dict()
|
||||
self.paramsExtern = dict()
|
||||
self.design = design
|
||||
self.paramsExtern["def_out"] = False
|
||||
|
||||
self.params["adjustToSite"] = False
|
||||
self.params["coreMarginsBy"] = False
|
||||
self.params["dieSizeByIoHeight"] = False
|
||||
|
|
@ -25,37 +23,42 @@ class InnovusFloorplan():
|
|||
self.params["site"] = False
|
||||
self.params["siteOnly"] = False
|
||||
|
||||
def setParams(self, param, value):
|
||||
if self.params.get(param) != None:
|
||||
self.params[param] = value
|
||||
elif self.paramsExtern.get(param) != None:
|
||||
self.paramsExtern[param] = value
|
||||
def setParams(self, param, optional):
|
||||
if self.params.get(param) is not None:
|
||||
self.params[param] = optional
|
||||
else:
|
||||
assert False, 'Unknown param'
|
||||
|
||||
def getObjHDL(self):
|
||||
obj_path = util.getObjPath(self.design)
|
||||
obj_hdl = os.path.join(obj_path, self.design.top_name + ".vh")
|
||||
obj_path = util.getObjPath(self.design, "Cadence")
|
||||
obj_hdl = obj_path + "/" + self.design.top_name + ".vh"
|
||||
return obj_hdl
|
||||
|
||||
def getObjSDC(self):
|
||||
obj_path = util.getObjPath(self.design)
|
||||
obj_sdc = os.path.join(obj_path, self.design.top_name + ".sdc")
|
||||
obj_path = util.getObjPath(self.design, "Cadence")
|
||||
obj_sdc = obj_path + "/" + self.design.top_name + ".sdc"
|
||||
return obj_sdc
|
||||
|
||||
def getObjMMMC(self):
|
||||
obj_path = util.getObjPath(self.design)
|
||||
mmmc_path = os.path.join(obj_path, "flow.view")
|
||||
return mmmc_path
|
||||
obj_path = util.getObjPath(self.design, "Cadence")
|
||||
obj_mmmc = "{" + obj_path + "/" + util.getMmmc(self.design) + "}"
|
||||
return obj_mmmc
|
||||
|
||||
def getLEF(self):
|
||||
lef_path = util.getLefPath(self.design, "Cadence")
|
||||
lef_file = lef_path + "/" + util.getLef(self.design)
|
||||
return lef_file
|
||||
|
||||
def config(self, design, tcl_file):
|
||||
tcl_path = util.getScriptPath(self.design)
|
||||
tcl = open(os.path.join(tcl_path, tcl_file + ".tcl"), 'w', encoding='utf-8')
|
||||
tcl_path = util.getScriptPath(self.design, "Cadence")
|
||||
obj_path = util.getObjPath(self.design, "Cadence")
|
||||
lef_path = util.getLefPath(self.design, "Cadence")
|
||||
|
||||
# tcl_path = "."
|
||||
tcl = open(tcl_path + "/" + tcl_file + ".tcl", 'w', encoding='utf-8')
|
||||
#init design
|
||||
util.createMMMC(self.design, self.getObjMMMC())
|
||||
tcl.write("set init_mmmc_file {%s}\n" % self.getObjMMMC())
|
||||
tcl.write("set init_lef_file %s\n" % self.design.lef_input)
|
||||
tcl.write("set init_mmmc_file %s\n" % self.getObjMMMC())
|
||||
tcl.write("set init_lef_file %s\n" % self.getLEF())
|
||||
tcl.write("set init_verilog %s\n" % self.getObjHDL()) # need to specified
|
||||
tcl.write('set init_gnd_net "VSS"\n')
|
||||
tcl.write('set init_pwr_net "VDD"\n')
|
||||
|
|
@ -68,8 +71,4 @@ class InnovusFloorplan():
|
|||
tcl.write(" -%s %s"%(param, self.params[param]))
|
||||
tcl.write("\n")
|
||||
|
||||
if self.paramsExtern["def_out"]:
|
||||
# tcl.write("set dbgLefDefOutVersion 5.8\ndefOut -netlist %s_after_fp.def\n" % self.design.top_name)
|
||||
tcl.write("defOut -netlist %s_after_fp.def\n" % self.design.top_name)
|
||||
|
||||
tcl.close()
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
import os
|
||||
import sys
|
||||
sys.path.append("../..")
|
||||
import util
|
||||
|
||||
|
||||
class InnovusPDN():
|
||||
def __init__(self, design):
|
||||
self.params = dict()
|
||||
|
|
@ -14,8 +14,9 @@ class InnovusPDN():
|
|||
assert False, 'Unknown param'
|
||||
|
||||
def config(self, design, tcl_file):
|
||||
tcl_path = util.getScriptPath(self.design)
|
||||
tcl = open(os.path.join(tcl_path, tcl_file + ".tcl"), 'w', encoding='utf-8')
|
||||
tcl_path = util.getScriptPath(self.design, "Cadence")
|
||||
# tcl_path = "."
|
||||
tcl = open(tcl_path + "/" + tcl_file + ".tcl", 'w', encoding='utf-8')
|
||||
|
||||
tcl.write('globalNetConnect VDD -type pgpin -pin VDD -inst * -verbose\n')
|
||||
tcl.write('globalNetConnect VSS -type pgpin -pin VSS -inst * -verbose\n')
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
import sys
|
||||
sys.path.append("../..")
|
||||
import util
|
||||
|
||||
class InnovusPlace(object):
|
||||
def __init__(self, design):
|
||||
self.design = design
|
||||
self.params = dict()
|
||||
self.params['concurrent_macros'] = False
|
||||
self.params['incremental'] = False
|
||||
self.params['noPrePlaceOpt'] = False
|
||||
|
||||
def setParams(self, param):
|
||||
if self.params.get(param) == None:
|
||||
print('[error] unknown param')
|
||||
else:
|
||||
self.params[param] = True
|
||||
|
||||
def config(self, design, tcl_file):
|
||||
tcl_path = util.getScriptPath(self.design, "Cadence")
|
||||
ret = 'place_design'
|
||||
for i in self.params:
|
||||
if self.params[i] == True:
|
||||
ret = ret + " -" + i
|
||||
|
||||
tcl = open(tcl_path + "/" + tcl_file + ".tcl", 'w', encoding = 'utf-8')
|
||||
tcl.writelines(ret)
|
||||
tcl.close()
|
||||
|
||||
return ret
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
import sys
|
||||
sys.path.append("../..")
|
||||
import util
|
||||
|
||||
class InnovusRoute():
|
||||
def __init__(self, design):
|
||||
self.design = design
|
||||
self.params = dict()
|
||||
self.paramsPassive = dict()
|
||||
self.params['highFrequency'] = False
|
||||
self.params['viaPillarOpt'] = False
|
||||
|
||||
self.paramsPassive['clockEco'] = False
|
||||
self.paramsPassive['trackOpt'] = False
|
||||
self.paramsPassive['idealClock'] = False
|
||||
self.paramsPassive['viaOpt'] = False
|
||||
self.paramsPassive['wireOpt'] = False
|
||||
|
||||
self.paramsPassive['placementCheck'] = False
|
||||
self.paramsPassive['noPlacementCheck'] = False
|
||||
|
||||
self.paramsPassive['globalDetail'] = False
|
||||
self.paramsPassive['detail'] = False
|
||||
|
||||
self.params['passiveFill'] = False
|
||||
|
||||
def setParams(self, param, optional):
|
||||
if self.params.get(param) is not None:
|
||||
self.params[param] = optional
|
||||
else:
|
||||
if self.paramsPassive.get(param) is not None:
|
||||
self.paramsPassive[param] = optional
|
||||
else:
|
||||
assert False, 'Unknown param'
|
||||
|
||||
def config(self, design, tcl_file):
|
||||
tcl_path = util.getScriptPath(self.design, "Cadence")
|
||||
ret = 'routeDesign'
|
||||
for i in self.params:
|
||||
if self.params[i]:
|
||||
ret = ret + " -" + i
|
||||
|
||||
assert not (self.paramsPassive['placementCheck'] and self.paramsPassive['noPlacementCheck']),\
|
||||
'Option -placementCheck and -noPlacementCheck are mutually exclusive.'
|
||||
assert not (self.paramsPassive['globalDetail'] and self.paramsPassive['detail']),\
|
||||
'Option -globalDetail and -detail are mutually exclusive.'
|
||||
|
||||
if not self.params['passiveFill']:
|
||||
for i in self.paramsPassive:
|
||||
if self.paramsPassive[i]:
|
||||
ret = ret + " -" + i
|
||||
|
||||
tcl = open(tcl_path + "/" + tcl_file + ".tcl", 'w', encoding='utf-8')
|
||||
tcl.writelines(ret)
|
||||
tcl.close()
|
||||
|
||||
return ret
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
import sys
|
||||
sys.path.append("../..")
|
||||
import util
|
||||
'''
|
||||
class Params():
|
||||
def __init__(self, typ, name, value, optional = False):
|
||||
self.type = typ
|
||||
self.name = name
|
||||
self.range = []
|
||||
self.value = value
|
||||
self.optional = optional
|
||||
|
||||
def check_valid(self):
|
||||
return True
|
||||
'''
|
||||
|
||||
class GenusSynth():
|
||||
def __init__(self, design):
|
||||
self.params = dict()
|
||||
self.params["effort"] = "medium"
|
||||
self.params["is_incremental"] = True
|
||||
self.params["spatial"] = False
|
||||
self.design = design
|
||||
#self.design.obj_hdl = design.obj_path + "/" + design.top_name + ".vh"
|
||||
#self.design.obj_sdc = design.obj_path + "/" + design.top_name + "_synth.sdc"
|
||||
#self.design.rpt_gates = design.rpt_path + "/" + "gates_synth.rpt"
|
||||
#self.design.rpt_timing = design.rpt_path + "/" + "timing_synth.rpt"
|
||||
#self.design.rpt_power = design.rpt_path + "/" + "power_synth.rpt"
|
||||
|
||||
def getObjHDL(self):
|
||||
obj_path = util.getObjPath(self.design, "Cadence")
|
||||
obj_hdl = obj_path + "/" + self.design.top_name + ".vh"
|
||||
return obj_hdl
|
||||
|
||||
def getObjSDC(self):
|
||||
obj_path = util.getObjPath(self.design, "Cadence")
|
||||
obj_sdc = obj_path + "/" + self.design.top_name + ".sdc"
|
||||
return obj_sdc
|
||||
|
||||
def getRptGates(self):
|
||||
rpt_path = util.getRptPath(self.design, "Cadence")
|
||||
rpt_gates = rpt_path + "/" + "gates_synth.rpt"
|
||||
return rpt_gates
|
||||
|
||||
def getRptTiming(self):
|
||||
rpt_path = util.getRptPath(self.design, "Cadence")
|
||||
rpt_timing = rpt_path + "/" + "timing_synth.rpt"
|
||||
return rpt_timing
|
||||
|
||||
def getRptPower(self):
|
||||
rpt_path = util.getRptPath(self.design, "Cadence")
|
||||
rpt_power = rpt_path + "/" + "gates_synth.rpt"
|
||||
return rpt_power
|
||||
|
||||
def setParams(self, param, optional):
|
||||
if self.params.get(param) is not None:
|
||||
self.params[param] = optional
|
||||
else:
|
||||
assert False, 'Unknown param'
|
||||
|
||||
def config(self, design, tcl_file):
|
||||
rtl_file = util.getHDL(self.design)
|
||||
lib_file = util.getLib(self.design)
|
||||
hdl_path = util.getHDLPath(self.design, "Cadence")
|
||||
lib_path = util.getLibPath(self.design, "Cadence")
|
||||
|
||||
#tcl = open(tcl_file + ".tcl", 'w', encoding='utf-8')
|
||||
tcl_path = util.getScriptPath(self.design, "Cadence")
|
||||
tcl = open(tcl_path + "/" + tcl_file + ".tcl", 'w', encoding='utf-8')
|
||||
|
||||
#tcl.write('set hdl_files %s\n'%(self.design.rtl_file))
|
||||
tcl.write('set hdl_files {%s}\n'%(rtl_file))
|
||||
tcl.write('set DESIGN %s\n'%(self.design.top_name))
|
||||
tcl.write('set clkpin %s\n'%(self.design.clk_name))
|
||||
tcl.write('set delay %d\n'%(self.design.delay))
|
||||
#tcl.write('set_attribute hdl_search_path %s\n'%(self.design.hdl_path))
|
||||
#tcl.write('set_attribute lib_search_path %s\n'%(self.design.lib_path))
|
||||
tcl.write('set_attribute hdl_search_path %s\n'%(hdl_path))
|
||||
tcl.write('set_attribute lib_search_path %s\n'%(lib_path))
|
||||
tcl.write('set_attribute information_level 6 \n')
|
||||
tcl.write('set_attribute library %s\n'%(lib_file))
|
||||
tcl.write('read_hdl ${hdl_files} \n')
|
||||
tcl.write('elaborate $DESIGN \n')
|
||||
tcl.write('set clock [define_clock -period ${delay} -name ${clkpin} [clock_ports]]\n')
|
||||
tcl.write('external_delay -input 0 -clock clk [find / -port ports_in/*]\n')
|
||||
tcl.write('external_delay -output 0 -clock clk [find / -port ports_out/*]\n')
|
||||
tcl.write('dc::set_clock_transition .4 clk\n')
|
||||
tcl.write('check_design -unresolved\n')
|
||||
tcl.write('report timing -lint\n')
|
||||
|
||||
ret = 'synthesize -to_mapped'
|
||||
|
||||
for i in self.params:
|
||||
if self.params[i]:
|
||||
ret = ret + " -" + i
|
||||
|
||||
tcl.write(ret + '\n')
|
||||
|
||||
#tcl.write("report timing > %s\n"%(self.design.rpt_timing))
|
||||
#tcl.write('report gates > %s\n'%(self.design.rpt_gates))
|
||||
#tcl.write('report power > %s\n'%(self.design.rpt_power))
|
||||
#tcl.write('write_hdl -mapped > %s\n'%(self.design.obj_hdl))
|
||||
#tcl.write('write_sdc > %s\n'%(self.design.obj_sdc))
|
||||
|
||||
tcl.write("report timing > %s\n"%(self.getRptTiming()))
|
||||
tcl.write('report gates > %s\n'%(self.getRptGates()))
|
||||
tcl.write('report power > %s\n'%(self.getRptPower()))
|
||||
tcl.write('write_hdl -mapped > %s\n'%(self.getObjHDL()))
|
||||
tcl.write('write_sdc > %s\n'%(self.getObjSDC()))
|
||||
|
||||
tcl.close()
|
||||
|
||||
'''
|
||||
class Output(object):
|
||||
|
||||
def __init__(self, design):
|
||||
pass
|
||||
|
||||
def config(self, file_name):
|
||||
f = open(file_name + ".tcl", "w")
|
||||
# to-do
|
||||
f.close()
|
||||
'''
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
import sys
|
||||
sys.path.append("../../..")
|
||||
import util
|
||||
|
||||
class YosysSynth():
|
||||
def __init__(self, design):
|
||||
self.params = dict()
|
||||
self.design = design
|
||||
|
||||
def getObjHDL(self):
|
||||
obj_path = util.getObjPath(self.design, "Yosys")
|
||||
obj_hdl = obj_path + "/" + self.design.top_name + ".v"
|
||||
return obj_hdl
|
||||
|
||||
def getObjSDC(self):
|
||||
obj_path = util.getObjPath(self.design, "Yosys")
|
||||
obj_sdc = obj_path + "/" + self.design.top_name + ".sdc"
|
||||
return obj_sdc
|
||||
|
||||
def getRptGates(self):
|
||||
rpt_path = util.getRptPath(self.design, "Yosys")
|
||||
rpt_gates = rpt_path + "/" + "gates_synth.rpt"
|
||||
return rpt_gates
|
||||
|
||||
def getRptTiming(self):
|
||||
rpt_path = util.getRptPath(self.design, "Yosys")
|
||||
rpt_timing = rpt_path + "/" + "timing_synth.rpt"
|
||||
return rpt_timing
|
||||
|
||||
def getRptPower(self):
|
||||
rpt_path = util.getRptPath(self.design, "Yosys")
|
||||
rpt_power = rpt_path + "/" + "gates_synth.rpt"
|
||||
return rpt_power
|
||||
|
||||
def setParams(self, param, optional):
|
||||
if self.params.get(param) is not None:
|
||||
self.params[param] = optional
|
||||
else:
|
||||
assert False, 'Unknown param'
|
||||
|
||||
def config(self, design, tcl_file):
|
||||
rtl_file = util.getHDL(self.design)
|
||||
lib_file = util.getLib(self.design)
|
||||
#top_name = self.design.top_name
|
||||
hdl_path = util.getHDLPath(self.design, "Yosys")
|
||||
lib_path = util.getLibPath(self.design, "Yosys")
|
||||
|
||||
tcl_path = util.getScriptPath(self.design, "Yosys")
|
||||
tcl = open(tcl_path + "/" + tcl_file + ".ys", 'w', encoding = 'utf-8')
|
||||
|
||||
tcl.write('read -sv %s\n'%(hdl_path + "/" + rtl_file))
|
||||
tcl.write('hierarchy -top %s\n'%(self.design.top_name))
|
||||
tcl.write('proc; opt; techmap; opt\n')
|
||||
tcl.write('write_verilog %s\n'%(self.getObjHDL()))
|
||||
|
||||
tcl.close()
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
class MySubFlow(object):
|
||||
def __init__(self):
|
||||
self.ops = []
|
||||
|
||||
def flow(self):
|
||||
op_syn = opsrc.op.logiccommander
|
||||
self.ops.append(op_syn)
|
||||
|
||||
|
||||
class MyFlow(object):
|
||||
|
||||
def __init__(self):
|
||||
self.ops = []
|
||||
self.des_list = []
|
||||
|
||||
|
||||
def flow(self):
|
||||
des_list = op.min_cut_partition(design)
|
||||
|
||||
for x in des_list:
|
||||
sub_flow = MySubFlow()
|
||||
sub_ops = sub_flow.ops
|
||||
ops.append(sub_ops)
|
||||
|
||||
#merge?
|
||||
|
||||
|
||||
op_floorplan = cds.op.innovus.floorplan
|
||||
ops.append(op_floorplan)
|
||||
|
||||
op_place = opsrc.op.dreamplace
|
||||
ops.append(op_place)
|
||||
|
||||
op_cts = cds.op.cts
|
||||
ops.append(op_place)
|
||||
|
||||
op_route = cds.op.route
|
||||
ops.append(op_place)
|
||||
|
||||
op_drc = cds.op.innovus.op_drc
|
||||
ops.append(op_drc)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
class MySubFlow(object):
|
||||
def __init__(self):
|
||||
self.ops = []
|
||||
|
||||
def flow(self):
|
||||
op_cts = cds.op.cts
|
||||
self.ops.append(op_cts)
|
||||
op_route = cds.op.route
|
||||
self.ops.append(op_route)
|
||||
|
||||
class MyFlow(object):
|
||||
|
||||
def __init__(self):
|
||||
self.ops = []
|
||||
self.des_list = []
|
||||
|
||||
|
||||
def flow(self):
|
||||
des_list = op.min_cut_partition(design)
|
||||
|
||||
op_syn = cds.op.genus
|
||||
ops.append(op_syn)
|
||||
|
||||
op_floorplan = cds.op.innovus.floorplan
|
||||
ops.append(op_floorplan)
|
||||
|
||||
op_place = opsrc.op.dreamplace
|
||||
ops.append(op_place)
|
||||
|
||||
for x in des_list:
|
||||
sub_flow = MySubFlow()
|
||||
sub_ops = sub_flow.ops
|
||||
ops.append(sub_ops)
|
||||
|
||||
op_drc = cds.op.innovus.op_drc
|
||||
ops.append(op_drc)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1 @@
|
|||
import numpy
|
||||
95
config.py
95
config.py
|
|
@ -1,95 +0,0 @@
|
|||
import configparser
|
||||
from flow import MyFlow
|
||||
from designcfg import Design
|
||||
import os
|
||||
|
||||
|
||||
class Config:
|
||||
"""
|
||||
Parse the config file
|
||||
Input: config file
|
||||
Output: (list)[(Design1, MyFlow1), ..., (Designx, MyFlowx)]
|
||||
"""
|
||||
def __init__(self, config_file):
|
||||
self.config = configparser.ConfigParser()
|
||||
try:
|
||||
self.config.read(config_file)
|
||||
except:
|
||||
print("Error: Fail to read config file %s" % config_file)
|
||||
# List of different sections (flows) of the .ini file
|
||||
self.multi_flows = self.config.sections()
|
||||
self.cocoon_home = os.getcwd()
|
||||
self.config_dir = os.path.dirname(os.path.abspath(config_file))
|
||||
|
||||
def parse(self):
|
||||
flows = []
|
||||
for flow_name in self.multi_flows:
|
||||
flows.append((self.createDesign(flow_name), self.createFlow(flow_name), flow_name))
|
||||
return flows
|
||||
|
||||
def createDesign(self, sec_name):
|
||||
design = Design()
|
||||
sec = self.config[sec_name]
|
||||
design.top_name = sec.get('design_name')
|
||||
|
||||
assert sec.get('lib_name'), "Argument lib_name is required!\n"
|
||||
design.lib_name = sec.get('lib_name')
|
||||
|
||||
design.is_Chisel_design = sec.getboolean('is_Chisel_design')
|
||||
design.rtl_input = sec.get('rtl_input')
|
||||
if not os.path.isabs(design.rtl_input): # Relative path
|
||||
design.rtl_input = os.path.join(self.config_dir, design.rtl_input)
|
||||
|
||||
design.Chisel_input = sec.get('Chisel_input')
|
||||
if not os.path.isabs(design.Chisel_input): # Relative path
|
||||
design.Chisel_input = os.path.join(self.config_dir, design.Chisel_input)
|
||||
|
||||
design.result_dir = sec.get('result_dir')
|
||||
if not os.path.isabs(design.result_dir): # Relative path
|
||||
design.result_dir = os.path.join(self.config_dir, design.result_dir)
|
||||
|
||||
design.lef_input = sec.get('lef_input')
|
||||
if not os.path.isabs(design.lef_input): # Relative path
|
||||
design.lef_input = os.path.join(self.config_dir, design.lef_input)
|
||||
|
||||
design.liberty_input = sec.get('liberty_input')
|
||||
if not os.path.isabs(design.liberty_input): # Relative path
|
||||
design.liberty_input = os.path.join(self.config_dir, design.liberty_input)
|
||||
|
||||
design.clk_name = sec.get('clk_name')
|
||||
design.delay = sec.getint('delay')
|
||||
|
||||
if design.is_Chisel_design:
|
||||
verbose = sec.getboolean('verbose')
|
||||
design.Chisel2RTL(verbose)
|
||||
|
||||
return design
|
||||
|
||||
def createFlow(self, sec_name):
|
||||
flow = MyFlow()
|
||||
sec = self.config[sec_name]
|
||||
|
||||
assert sec.get('flow'), "Argument flow is required!\n"
|
||||
flow.flow = eval(sec.get('flow'))
|
||||
|
||||
assert sec.get('n_iter_IFT'), "Argument n_iter_IFT is required!\n"
|
||||
flow.n_iter_IFT = sec.getint('n_iter_IFT')
|
||||
|
||||
assert not ((flow.flow['synth'] == 'yosys') and (flow.n_iter_IFT > 0)), "IFT cannot work with Yosys, try GenusSynth instead.\n"
|
||||
|
||||
flow.verbose = sec.getboolean('verbose')
|
||||
|
||||
if sec.get('cadence_version'):
|
||||
flow.cadence_version = sec.get('cadence_version')
|
||||
|
||||
flow.yosys_bin_path = os.path.join(self.cocoon_home, 'thirdparty/yosys/build/')
|
||||
flow.dreamplace_bin_path = os.path.join(self.cocoon_home, 'thirdparty/DREAMPlace/install/dreamplace/Placer.py')
|
||||
|
||||
flow.config()
|
||||
return flow
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,26 @@
|
|||
module behav_counter(d, clk, clear, load, up_down, qd);
|
||||
|
||||
input [7:0] d;
|
||||
input clk;
|
||||
input clear;
|
||||
input load;
|
||||
input up_down;
|
||||
output [7:0] qd;
|
||||
|
||||
reg [7:0] cnt;
|
||||
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (!clear)
|
||||
cnt <= 8'h00;
|
||||
else if (load)
|
||||
cnt <= d;
|
||||
else if (up_down)
|
||||
cnt <= cnt + 1;
|
||||
else
|
||||
cnt <= cnt - 1;
|
||||
end
|
||||
|
||||
assign qd = cnt;
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,370 @@
|
|||
# ####################################################################
|
||||
|
||||
# Created by Genus(TM) Synthesis Solution 19.12-s121_1 on Sat Aug 01 20:42:27 CST 2020
|
||||
|
||||
# ####################################################################
|
||||
|
||||
set sdc_version 2.0
|
||||
|
||||
set_units -capacitance 1000fF
|
||||
set_units -time 1000ps
|
||||
|
||||
# Set the current design
|
||||
current_design TopModuleWrapper
|
||||
|
||||
create_clock -name "clk" -period 10.0 -waveform {0.0 5.0} [get_ports clock]
|
||||
set_clock_transition 0.4 [get_clocks clk]
|
||||
set_clock_gating_check -setup 0.0
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[0]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[1]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[2]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[3]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[4]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[5]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[6]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[7]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[8]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[9]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[10]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[11]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[12]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[13]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[14]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[15]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[16]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[17]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[18]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[19]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[20]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[21]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[22]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[23]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[24]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[25]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[26]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[27]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[28]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[29]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[30]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[31]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[0]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[1]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[2]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[3]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[4]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[5]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[6]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[7]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[8]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[9]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[10]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[11]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[12]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[13]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[14]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[15]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[16]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[17]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[18]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[19]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[20]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[21]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[22]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[23]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[24]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[25]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[26]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[27]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[28]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[29]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[30]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[31]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[0]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[1]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[2]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[3]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[4]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[5]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[6]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[7]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[8]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[9]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[10]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[11]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[12]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[13]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[14]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[15]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[16]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[17]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[18]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[19]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[20]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[21]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[22]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[23]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[24]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[25]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[26]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[27]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[28]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[29]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[30]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[31]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[0]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[1]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[2]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[3]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[4]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[5]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[6]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[7]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[8]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[9]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[10]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[11]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[12]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[13]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[14]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[15]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[16]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[17]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[18]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[19]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[20]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[21]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[22]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[23]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[24]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[25]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[26]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[27]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[28]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[29]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[30]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[31]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_II[0]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_II[1]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_II[2]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports io_en]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_LSUnitID[0]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_LSUnitID[1]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports io_deqEnLSU]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports io_enqEnLSU]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports io_startLSU]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_lenLSU[0]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_lenLSU[1]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_lenLSU[2]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_lenLSU[3]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_lenLSU[4]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_lenLSU[5]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_lenLSU[6]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_lenLSU[7]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_baseLSU[0]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_baseLSU[1]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_baseLSU[2]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_baseLSU[3]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_baseLSU[4]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_baseLSU[5]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_baseLSU[6]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_baseLSU[7]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports io_streamOutLSU_ready]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[0]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[1]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[2]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[3]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[4]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[5]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[6]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[7]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[8]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[9]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[10]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[11]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[12]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[13]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[14]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[15]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[16]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[17]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[18]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[19]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[20]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[21]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[22]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[23]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[24]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[25]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[26]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[27]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[28]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[29]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[30]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[31]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports io_streamInLSU_valid]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports reset]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports clock]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[0]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[1]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[2]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[3]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[4]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[5]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[6]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[7]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[8]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[9]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[10]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[11]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[12]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[13]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[14]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[15]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[16]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[17]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[18]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[19]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[20]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[21]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[22]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[23]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[24]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[25]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[26]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[27]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[28]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[29]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[30]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[31]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[0]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[1]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[2]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[3]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[4]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[5]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[6]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[7]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[8]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[9]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[10]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[11]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[12]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[13]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[14]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[15]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[16]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[17]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[18]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[19]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[20]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[21]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[22]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[23]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[24]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[25]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[26]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[27]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[28]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[29]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[30]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[31]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[0]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[1]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[2]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[3]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[4]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[5]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[6]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[7]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[8]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[9]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[10]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[11]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[12]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[13]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[14]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[15]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[16]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[17]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[18]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[19]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[20]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[21]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[22]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[23]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[24]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[25]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[26]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[27]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[28]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[29]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[30]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[31]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[0]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[1]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[2]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[3]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[4]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[5]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[6]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[7]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[8]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[9]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[10]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[11]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[12]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[13]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[14]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[15]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[16]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[17]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[18]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[19]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[20]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[21]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[22]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[23]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[24]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[25]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[26]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[27]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[28]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[29]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[30]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[31]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports io_idleLSU]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[0]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[1]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[2]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[3]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[4]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[5]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[6]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[7]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[8]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[9]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[10]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[11]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[12]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[13]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[14]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[15]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[16]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[17]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[18]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[19]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[20]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[21]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[22]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[23]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[24]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[25]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[26]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[27]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[28]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[29]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[30]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[31]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports io_streamOutLSU_valid]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports io_streamInLSU_ready]
|
||||
set_wire_load_mode "enclosed"
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
============================================================
|
||||
Generated by: Genus(TM) Synthesis Solution 19.12-s121_1
|
||||
Generated on: Aug 01 2020 08:42:19 pm
|
||||
Module: TopModuleWrapper
|
||||
Technology library: gscl45nm
|
||||
Operating conditions: typical (balanced_tree)
|
||||
Wireload mode: enclosed
|
||||
Area mode: timing library
|
||||
============================================================
|
||||
|
||||
|
||||
Type Instances Area Area %
|
||||
--------------------------------------
|
||||
sequential 37256 0.000 0.0
|
||||
inverter 6133 0.000 0.0
|
||||
logic 38506 0.000 0.0
|
||||
physical_cells 0 0.000 0.0
|
||||
--------------------------------------
|
||||
total 81895 0.000 0.0
|
||||
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
Instance: /TopModuleWrapper
|
||||
Power Unit: W
|
||||
PDB Frames: /stim#0/frame#0
|
||||
-------------------------------------------------------------------------
|
||||
Category Leakage Internal Switching Total Row%
|
||||
-------------------------------------------------------------------------
|
||||
memory 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
register 2.04824e-03 2.28401e-02 0.00000e+00 2.48883e-02 84.90%
|
||||
latch 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
logic 5.43527e-04 3.88212e-03 0.00000e+00 4.42565e-03 15.10%
|
||||
bbox 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
clock 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
pad 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
pm 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
-------------------------------------------------------------------------
|
||||
Subtotal 2.59177e-03 2.67222e-02 0.00000e+00 2.93140e-02 100.00%
|
||||
Percentage 8.84% 91.16% 0.00% 100.00% 100.00%
|
||||
-------------------------------------------------------------------------
|
||||
|
|
@ -0,0 +1,529 @@
|
|||
============================================================
|
||||
Generated by: Genus(TM) Synthesis Solution 19.12-s121_1
|
||||
Generated on: Aug 01 2020 08:42:16 pm
|
||||
Module: TopModuleWrapper
|
||||
Technology library: gscl45nm
|
||||
Operating conditions: typical (balanced_tree)
|
||||
Wireload mode: enclosed
|
||||
Area mode: timing library
|
||||
============================================================
|
||||
|
||||
Pin Type Fanout Load Slew Delay Arrival
|
||||
(fF) (ps) (ps) (ps)
|
||||
------------------------------------------------------------------------------------------------
|
||||
(clock clk) launch 0 R
|
||||
topModule
|
||||
configController_cycleReg_reg[0]/clk 400 0 R
|
||||
configController_cycleReg_reg[0]/q (u) unmapped_d_flop 11 46.2 0 +204 204 F
|
||||
g59978/in_0 +0 204
|
||||
g59978/z (u) unmapped_not 6 27.0 0 +60 264 R
|
||||
g60340/in_0 +0 264
|
||||
g60340/z (u) unmapped_nand3 2 8.4 0 +62 326 F
|
||||
g737/in_0 +0 326
|
||||
g737/z (u) unmapped_nor2 2 9.0 0 +51 376 R
|
||||
topDispatch_mux_2797_23_g52184/sel8 +0 376
|
||||
topDispatch_mux_2797_23_g52184/z (u) unmapped_mux18 468 2106.0 0 +245 621 R
|
||||
RegisterFiles/io_configuration[27]
|
||||
g6723/in_0 +0 621
|
||||
g6723/z (u) unmapped_not 3 12.6 0 +49 670 F
|
||||
g6747/in_1 +0 670
|
||||
g6747/z (u) unmapped_nor3 1 4.5 0 +52 722 R
|
||||
g6748/in_0 +0 722
|
||||
g6748/z (u) unmapped_not 2 8.4 0 +42 764 F
|
||||
g6809/in_0 +0 764
|
||||
g6809/z (u) unmapped_nor2 32 144.0 0 +104 868 R
|
||||
mux_912_22_g62/sel3 +0 868
|
||||
mux_912_22_g62/z (u) unmapped_mux18 7 31.5 0 +160 1029 R
|
||||
RegisterFiles/io_outs_5[1]
|
||||
g73311/in_0 +0 1029
|
||||
g73311/z (u) unmapped_and2 1 4.5 0 +41 1069 R
|
||||
g73313/in_0 +0 1069
|
||||
g73313/z (u) unmapped_or2 1 4.5 0 +41 1110 R
|
||||
g73314/in_1 +0 1110
|
||||
g73314/z (u) unmapped_or2 2 9.0 0 +51 1161 R
|
||||
Alu_3_syncScheduleController_regNextN/io_input[1]
|
||||
mux_30_19_g317/data0 +0 1161
|
||||
mux_30_19_g317/z (u) unmapped_mux8 111 499.5 0 +184 1344 R
|
||||
Alu_3_syncScheduleController_regNextN/io_out[1]
|
||||
Alu_3_div_202_57/B[1]
|
||||
g765/in_0 +0 1344
|
||||
g765/z (u) unmapped_nor2 2 8.4 0 +51 1395 F
|
||||
g234/in_0 +0 1395
|
||||
g234/z (u) unmapped_not 2 9.0 0 +42 1437 R
|
||||
g69/in_1 +0 1437
|
||||
g69/z (u) unmapped_nand2 1 4.2 0 +41 1478 F
|
||||
g70/in_1 +0 1478
|
||||
g70/z (u) unmapped_nand2 3 13.5 0 +58 1535 R
|
||||
g275/in_1 +0 1535
|
||||
g275/z (u) unmapped_nand2 1 4.2 0 +41 1576 F
|
||||
g276/in_1 +0 1576
|
||||
g276/z (u) unmapped_nand2 5 22.5 0 +65 1641 R
|
||||
g339/in_0 +0 1641
|
||||
g339/z (u) unmapped_nand2 1 4.2 0 +41 1681 F
|
||||
g340/in_1 +0 1681
|
||||
g340/z (u) unmapped_nand2 9 40.5 0 +78 1759 R
|
||||
g409/in_1 +0 1759
|
||||
g409/z (u) unmapped_nand2 1 4.2 0 +41 1800 F
|
||||
g410/in_1 +0 1800
|
||||
g410/z (u) unmapped_nand2 17 76.5 0 +91 1891 R
|
||||
g486/in_0 +0 1891
|
||||
g486/z (u) unmapped_nand2 1 4.2 0 +41 1932 F
|
||||
g487/in_1 +0 1932
|
||||
g487/z (u) unmapped_nand2 1 4.5 0 +41 1972 R
|
||||
g570/in_0 +0 1972
|
||||
g570/z (u) unmapped_xnor2 2 8.4 0 +86 2059 F
|
||||
g964/in_1 +0 2059
|
||||
g964/z (u) unmapped_nor2 3 13.5 0 +58 2116 R
|
||||
g989/in_1 +0 2116
|
||||
g989/z (u) unmapped_nand2 5 21.0 0 +65 2181 F
|
||||
g1011/in_1 +0 2181
|
||||
g1011/z (u) unmapped_nor2 6 27.0 0 +69 2250 R
|
||||
g1033/in_1 +0 2250
|
||||
g1033/z (u) unmapped_nand2 1 4.2 0 +41 2290 F
|
||||
g1059/in_0 +0 2290
|
||||
g1059/z (u) unmapped_not 8 36.0 0 +68 2358 R
|
||||
g1060/in_1 +0 2358
|
||||
g1060/z (u) unmapped_nand2 1 4.2 0 +41 2399 F
|
||||
g1114/in_0 +0 2399
|
||||
g1114/z (u) unmapped_not 1 4.5 0 +32 2431 R
|
||||
g1063/in_1 +0 2431
|
||||
g1063/z (u) unmapped_nand2 3 12.6 0 +58 2488 F
|
||||
g4/in_1 +0 2488
|
||||
g4/z (u) unmapped_and2 2 8.4 0 +51 2539 F
|
||||
g1131/sel2 +0 2539
|
||||
g1131/z (u) unmapped_mux8 7 29.4 0 +139 2678 F
|
||||
g1337/in_0 +0 2678
|
||||
g1337/z (u) unmapped_nor2 3 13.5 0 +58 2735 R
|
||||
g1345/in_1 +0 2735
|
||||
g1345/z (u) unmapped_nor2 1 4.2 0 +41 2776 F
|
||||
g1363/in_0 +0 2776
|
||||
g1363/z (u) unmapped_nand2 1 4.5 0 +41 2816 R
|
||||
g1364/in_1 +0 2816
|
||||
g1364/z (u) unmapped_nand2 1 4.2 0 +41 2857 F
|
||||
g1392/in_0 +0 2857
|
||||
g1392/z (u) unmapped_nand2 1 4.5 0 +41 2898 R
|
||||
g1497/in_0 +0 2898
|
||||
g1497/z (u) unmapped_not 1 4.2 0 +32 2930 F
|
||||
g1418/in_1 +0 2930
|
||||
g1418/z (u) unmapped_nand2 1 4.5 0 +41 2971 R
|
||||
g1501/in_0 +0 2971
|
||||
g1501/z (u) unmapped_not 1 4.2 0 +32 3003 F
|
||||
g1456/in_0 +0 3003
|
||||
g1456/z (u) unmapped_nand2 1 4.5 0 +41 3044 R
|
||||
g1509/in_0 +0 3044
|
||||
g1509/z (u) unmapped_not 1 4.2 0 +32 3076 F
|
||||
g1458/in_0 +0 3076
|
||||
g1458/z (u) unmapped_nand2 3 13.5 0 +58 3133 R
|
||||
g15/in_0 +0 3133
|
||||
g15/z (u) unmapped_not 1 4.2 0 +32 3165 F
|
||||
g16/in_0 +0 3165
|
||||
g16/z (u) unmapped_and2 4 16.8 0 +63 3228 F
|
||||
g1729/sel2 +0 3228
|
||||
g1729/z (u) unmapped_mux8 7 29.4 0 +139 3367 F
|
||||
g1954/in_0 +0 3367
|
||||
g1954/z (u) unmapped_nor2 3 13.5 0 +58 3424 R
|
||||
g1966/in_1 +0 3424
|
||||
g1966/z (u) unmapped_nor2 1 4.2 0 +41 3465 F
|
||||
g1987/in_0 +0 3465
|
||||
g1987/z (u) unmapped_nand2 1 4.5 0 +41 3506 R
|
||||
g1988/in_1 +0 3506
|
||||
g1988/z (u) unmapped_nand2 3 12.6 0 +58 3563 F
|
||||
g2022/in_0 +0 3563
|
||||
g2022/z (u) unmapped_nand2 1 4.5 0 +41 3604 R
|
||||
g2023/in_1 +0 3604
|
||||
g2023/z (u) unmapped_nand2 1 4.2 0 +41 3644 F
|
||||
g2049/in_1 +0 3644
|
||||
g2049/z (u) unmapped_nand2 1 4.5 0 +41 3685 R
|
||||
g2133/in_0 +0 3685
|
||||
g2133/z (u) unmapped_not 1 4.2 0 +32 3717 F
|
||||
g2087/in_0 +0 3717
|
||||
g2087/z (u) unmapped_nand2 1 4.5 0 +41 3758 R
|
||||
g2141/in_0 +0 3758
|
||||
g2141/z (u) unmapped_not 1 4.2 0 +32 3790 F
|
||||
g2089/in_0 +0 3790
|
||||
g2089/z (u) unmapped_nand2 3 13.5 0 +58 3848 R
|
||||
g27/in_0 +0 3848
|
||||
g27/z (u) unmapped_not 1 4.2 0 +32 3880 F
|
||||
g28/in_0 +0 3880
|
||||
g28/z (u) unmapped_and2 6 25.2 0 +69 3948 F
|
||||
g2380/sel2 +0 3948
|
||||
g2380/z (u) unmapped_mux8 7 29.4 0 +139 4087 F
|
||||
g2621/in_0 +0 4087
|
||||
g2621/z (u) unmapped_nor2 3 13.5 0 +58 4145 R
|
||||
g2637/in_1 +0 4145
|
||||
g2637/z (u) unmapped_nor2 1 4.2 0 +41 4185 F
|
||||
g2661/in_0 +0 4185
|
||||
g2661/z (u) unmapped_nand2 1 4.5 0 +41 4226 R
|
||||
g2662/in_1 +0 4226
|
||||
g2662/z (u) unmapped_nand2 5 21.0 0 +65 4291 F
|
||||
g2700/in_0 +0 4291
|
||||
g2700/z (u) unmapped_nand2 1 4.5 0 +41 4331 R
|
||||
g2701/in_1 +0 4331
|
||||
g2701/z (u) unmapped_nand2 1 4.2 0 +41 4372 F
|
||||
g2727/in_1 +0 4372
|
||||
g2727/z (u) unmapped_nand2 1 4.5 0 +41 4413 R
|
||||
g2812/in_0 +0 4413
|
||||
g2812/z (u) unmapped_not 1 4.2 0 +32 4445 F
|
||||
g2765/in_0 +0 4445
|
||||
g2765/z (u) unmapped_nand2 1 4.5 0 +41 4486 R
|
||||
g2820/in_0 +0 4486
|
||||
g2820/z (u) unmapped_not 1 4.2 0 +32 4518 F
|
||||
g2767/in_0 +0 4518
|
||||
g2767/z (u) unmapped_nand2 3 13.5 0 +58 4575 R
|
||||
g39/in_0 +0 4575
|
||||
g39/z (u) unmapped_not 1 4.2 0 +32 4607 F
|
||||
g40/in_0 +0 4607
|
||||
g40/z (u) unmapped_and2 8 33.6 0 +76 4684 F
|
||||
g3075/sel2 +0 4684
|
||||
g3075/z (u) unmapped_mux8 7 29.4 0 +139 4822 F
|
||||
g3343/in_0 +0 4822
|
||||
g3343/z (u) unmapped_nor2 3 13.5 0 +58 4880 R
|
||||
g3363/in_1 +0 4880
|
||||
g3363/z (u) unmapped_nor2 1 4.2 0 +41 4920 F
|
||||
g3390/in_0 +0 4920
|
||||
g3390/z (u) unmapped_nand2 1 4.5 0 +41 4961 R
|
||||
g3391/in_1 +0 4961
|
||||
g3391/z (u) unmapped_nand2 5 21.0 0 +65 5026 F
|
||||
g3432/in_0 +0 5026
|
||||
g3432/z (u) unmapped_nand2 1 4.5 0 +41 5066 R
|
||||
g3433/in_1 +0 5066
|
||||
g3433/z (u) unmapped_nand2 3 12.6 0 +58 5124 F
|
||||
g3470/in_1 +0 5124
|
||||
g3470/z (u) unmapped_nand2 1 4.5 0 +41 5165 R
|
||||
g3471/in_1 +0 5165
|
||||
g3471/z (u) unmapped_nand2 1 4.2 0 +41 5205 F
|
||||
g3509/in_0 +0 5205
|
||||
g3509/z (u) unmapped_nand2 1 4.5 0 +41 5246 R
|
||||
g3565/in_0 +0 5246
|
||||
g3565/z (u) unmapped_not 1 4.2 0 +32 5278 F
|
||||
g3511/in_0 +0 5278
|
||||
g3511/z (u) unmapped_nand2 3 13.5 0 +58 5336 R
|
||||
g51/in_0 +0 5336
|
||||
g51/z (u) unmapped_not 1 4.2 0 +32 5368 F
|
||||
g52/in_0 +0 5368
|
||||
g52/z (u) unmapped_and2 10 42.0 0 +80 5448 F
|
||||
g3847/sel2 +0 5448
|
||||
g3847/z (u) unmapped_mux8 7 29.4 0 +139 5586 F
|
||||
g4131/in_0 +0 5586
|
||||
g4131/z (u) unmapped_nor2 3 13.5 0 +58 5644 R
|
||||
g4155/in_1 +0 5644
|
||||
g4155/z (u) unmapped_nor2 1 4.2 0 +41 5684 F
|
||||
g4185/in_0 +0 5684
|
||||
g4185/z (u) unmapped_nand2 1 4.5 0 +41 5725 R
|
||||
g4186/in_1 +0 5725
|
||||
g4186/z (u) unmapped_nand2 5 21.0 0 +65 5790 F
|
||||
g4231/in_0 +0 5790
|
||||
g4231/z (u) unmapped_nand2 1 4.5 0 +41 5831 R
|
||||
g4232/in_1 +0 5831
|
||||
g4232/z (u) unmapped_nand2 5 21.0 0 +65 5895 F
|
||||
g4269/in_1 +0 5895
|
||||
g4269/z (u) unmapped_nand2 1 4.5 0 +41 5936 R
|
||||
g4270/in_1 +0 5936
|
||||
g4270/z (u) unmapped_nand2 1 4.2 0 +41 5977 F
|
||||
g4308/in_0 +0 5977
|
||||
g4308/z (u) unmapped_nand2 1 4.5 0 +41 6017 R
|
||||
g4365/in_0 +0 6017
|
||||
g4365/z (u) unmapped_not 1 4.2 0 +32 6050 F
|
||||
g4310/in_0 +0 6050
|
||||
g4310/z (u) unmapped_nand2 3 13.5 0 +58 6107 R
|
||||
g63/in_0 +0 6107
|
||||
g63/z (u) unmapped_not 1 4.2 0 +32 6139 F
|
||||
g64/in_0 +0 6139
|
||||
g64/z (u) unmapped_and2 12 50.4 0 +83 6222 F
|
||||
g4663/sel2 +0 6222
|
||||
g4663/z (u) unmapped_mux8 7 29.4 0 +139 6361 F
|
||||
g4967/in_0 +0 6361
|
||||
g4967/z (u) unmapped_nor2 3 13.5 0 +58 6418 R
|
||||
g4995/in_1 +0 6418
|
||||
g4995/z (u) unmapped_nor2 1 4.2 0 +41 6459 F
|
||||
g5028/in_0 +0 6459
|
||||
g5028/z (u) unmapped_nand2 1 4.5 0 +41 6500 R
|
||||
g5029/in_1 +0 6500
|
||||
g5029/z (u) unmapped_nand2 5 21.0 0 +65 6565 F
|
||||
g5077/in_0 +0 6565
|
||||
g5077/z (u) unmapped_nand2 1 4.5 0 +41 6605 R
|
||||
g5078/in_1 +0 6605
|
||||
g5078/z (u) unmapped_nand2 7 29.4 0 +73 6678 F
|
||||
g5121/in_1 +0 6678
|
||||
g5121/z (u) unmapped_nand2 1 4.5 0 +41 6719 R
|
||||
g5122/in_1 +0 6719
|
||||
g5122/z (u) unmapped_nand2 1 4.2 0 +41 6759 F
|
||||
g5160/in_0 +0 6759
|
||||
g5160/z (u) unmapped_nand2 1 4.5 0 +41 6800 R
|
||||
g5217/in_0 +0 6800
|
||||
g5217/z (u) unmapped_not 1 4.2 0 +32 6832 F
|
||||
g5162/in_0 +0 6832
|
||||
g5162/z (u) unmapped_nand2 3 13.5 0 +58 6890 R
|
||||
g75/in_0 +0 6890
|
||||
g75/z (u) unmapped_not 1 4.2 0 +32 6922 F
|
||||
g76/in_0 +0 6922
|
||||
g76/z (u) unmapped_and2 14 58.8 0 +87 7008 F
|
||||
g5535/sel2 +0 7008
|
||||
g5535/z (u) unmapped_mux8 7 29.4 0 +139 7147 F
|
||||
g5859/in_0 +0 7147
|
||||
g5859/z (u) unmapped_nor2 3 13.5 0 +58 7205 R
|
||||
g5891/in_1 +0 7205
|
||||
g5891/z (u) unmapped_nor2 1 4.2 0 +41 7245 F
|
||||
g5927/in_0 +0 7245
|
||||
g5927/z (u) unmapped_nand2 1 4.5 0 +41 7286 R
|
||||
g5928/in_1 +0 7286
|
||||
g5928/z (u) unmapped_nand2 5 21.0 0 +65 7351 F
|
||||
g5980/in_0 +0 7351
|
||||
g5980/z (u) unmapped_nand2 1 4.5 0 +41 7391 R
|
||||
g5981/in_1 +0 7391
|
||||
g5981/z (u) unmapped_nand2 9 37.8 0 +78 7469 F
|
||||
g6026/in_1 +0 7469
|
||||
g6026/z (u) unmapped_nand2 1 4.5 0 +41 7510 R
|
||||
g6027/in_1 +0 7510
|
||||
g6027/z (u) unmapped_nand2 1 4.2 0 +41 7551 F
|
||||
g6065/in_0 +0 7551
|
||||
g6065/z (u) unmapped_nand2 1 4.5 0 +41 7592 R
|
||||
g6125/in_0 +0 7592
|
||||
g6125/z (u) unmapped_not 1 4.2 0 +32 7624 F
|
||||
g6067/in_0 +0 7624
|
||||
g6067/z (u) unmapped_nand2 3 13.5 0 +58 7681 R
|
||||
g87/in_0 +0 7681
|
||||
g87/z (u) unmapped_not 1 4.2 0 +32 7713 F
|
||||
g88/in_0 +0 7713
|
||||
g88/z (u) unmapped_and2 16 67.2 0 +90 7803 F
|
||||
g6463/sel2 +0 7803
|
||||
g6463/z (u) unmapped_mux8 7 29.4 0 +139 7942 F
|
||||
g6837/in_0 +0 7942
|
||||
g6837/z (u) unmapped_nor2 3 13.5 0 +58 7999 R
|
||||
g6873/in_1 +0 7999
|
||||
g6873/z (u) unmapped_nor2 1 4.2 0 +41 8040 F
|
||||
g6912/in_0 +0 8040
|
||||
g6912/z (u) unmapped_nand2 1 4.5 0 +41 8081 R
|
||||
g6913/in_1 +0 8081
|
||||
g6913/z (u) unmapped_nand2 5 21.0 0 +65 8145 F
|
||||
g6968/in_0 +0 8145
|
||||
g6968/z (u) unmapped_nand2 1 4.5 0 +41 8186 R
|
||||
g6969/in_1 +0 8186
|
||||
g6969/z (u) unmapped_nand2 9 37.8 0 +78 8264 F
|
||||
g7018/in_1 +0 8264
|
||||
g7018/z (u) unmapped_nand2 1 4.5 0 +41 8305 R
|
||||
g7019/in_1 +0 8305
|
||||
g7019/z (u) unmapped_nand2 3 12.6 0 +58 8362 F
|
||||
g7085/in_0 +0 8362
|
||||
g7085/z (u) unmapped_nand2 1 4.5 0 +41 8403 R
|
||||
g7086/in_1 +0 8403
|
||||
g7086/z (u) unmapped_nand2 1 4.2 0 +41 8444 F
|
||||
g7088/in_0 +0 8444
|
||||
g7088/z (u) unmapped_nand2 3 13.5 0 +58 8501 R
|
||||
g99/in_0 +0 8501
|
||||
g99/z (u) unmapped_not 1 4.2 0 +32 8533 F
|
||||
g100/in_0 +0 8533
|
||||
g100/z (u) unmapped_and2 18 75.6 0 +92 8625 F
|
||||
g7533/sel2 +0 8625
|
||||
g7533/z (u) unmapped_mux8 7 29.4 0 +139 8764 F
|
||||
g7923/in_0 +0 8764
|
||||
g7923/z (u) unmapped_nor2 3 13.5 0 +58 8821 R
|
||||
g7963/in_1 +0 8821
|
||||
g7963/z (u) unmapped_nor2 1 4.2 0 +41 8862 F
|
||||
g8005/in_0 +0 8862
|
||||
g8005/z (u) unmapped_nand2 1 4.5 0 +41 8903 R
|
||||
g8006/in_1 +0 8903
|
||||
g8006/z (u) unmapped_nand2 5 21.0 0 +65 8967 F
|
||||
g8065/in_0 +0 8967
|
||||
g8065/z (u) unmapped_nand2 1 4.5 0 +41 9008 R
|
||||
g8066/in_1 +0 9008
|
||||
g8066/z (u) unmapped_nand2 9 37.8 0 +78 9086 F
|
||||
g8115/in_1 +0 9086
|
||||
g8115/z (u) unmapped_nand2 1 4.5 0 +41 9127 R
|
||||
g8116/in_1 +0 9127
|
||||
g8116/z (u) unmapped_nand2 5 21.0 0 +65 9192 F
|
||||
g8182/in_0 +0 9192
|
||||
g8182/z (u) unmapped_nand2 1 4.5 0 +41 9232 R
|
||||
g8183/in_1 +0 9232
|
||||
g8183/z (u) unmapped_nand2 1 4.2 0 +41 9273 F
|
||||
g8185/in_0 +0 9273
|
||||
g8185/z (u) unmapped_nand2 3 13.5 0 +58 9330 R
|
||||
g111/in_0 +0 9330
|
||||
g111/z (u) unmapped_not 1 4.2 0 +32 9362 F
|
||||
g112/in_0 +0 9362
|
||||
g112/z (u) unmapped_and2 20 84.0 0 +94 9456 F
|
||||
g8647/sel2 +0 9456
|
||||
g8647/z (u) unmapped_mux8 7 29.4 0 +139 9595 F
|
||||
g9057/in_0 +0 9595
|
||||
g9057/z (u) unmapped_nor2 3 13.5 0 +58 9652 R
|
||||
g9101/in_1 +0 9652
|
||||
g9101/z (u) unmapped_nor2 1 4.2 0 +41 9693 F
|
||||
g9146/in_0 +0 9693
|
||||
g9146/z (u) unmapped_nand2 1 4.5 0 +41 9734 R
|
||||
g9147/in_1 +0 9734
|
||||
g9147/z (u) unmapped_nand2 5 21.0 0 +65 9798 F
|
||||
g9209/in_0 +0 9798
|
||||
g9209/z (u) unmapped_nand2 1 4.5 0 +41 9839 R
|
||||
g9210/in_1 +0 9839
|
||||
g9210/z (u) unmapped_nand2 9 37.8 0 +78 9917 F
|
||||
g9265/in_1 +0 9917
|
||||
g9265/z (u) unmapped_nand2 1 4.5 0 +41 9958 R
|
||||
g9266/in_1 +0 9958
|
||||
g9266/z (u) unmapped_nand2 7 29.4 0 +73 10031 F
|
||||
g9332/in_0 +0 10031
|
||||
g9332/z (u) unmapped_nand2 1 4.5 0 +41 10071 R
|
||||
g9333/in_1 +0 10071
|
||||
g9333/z (u) unmapped_nand2 1 4.2 0 +41 10112 F
|
||||
g9335/in_0 +0 10112
|
||||
g9335/z (u) unmapped_nand2 3 13.5 0 +58 10170 R
|
||||
g123/in_0 +0 10170
|
||||
g123/z (u) unmapped_not 1 4.2 0 +32 10202 F
|
||||
g124/in_0 +0 10202
|
||||
g124/z (u) unmapped_and2 22 92.4 0 +96 10297 F
|
||||
g9817/sel2 +0 10297
|
||||
g9817/z (u) unmapped_mux8 7 29.4 0 +139 10436 F
|
||||
g10247/in_0 +0 10436
|
||||
g10247/z (u) unmapped_nor2 3 13.5 0 +58 10493 R
|
||||
g10295/in_1 +0 10493
|
||||
g10295/z (u) unmapped_nor2 1 4.2 0 +41 10534 F
|
||||
g10343/in_0 +0 10534
|
||||
g10343/z (u) unmapped_nand2 1 4.5 0 +41 10575 R
|
||||
g10344/in_1 +0 10575
|
||||
g10344/z (u) unmapped_nand2 5 21.0 0 +65 10640 F
|
||||
g10410/in_0 +0 10640
|
||||
g10410/z (u) unmapped_nand2 1 4.5 0 +41 10680 R
|
||||
g10411/in_1 +0 10680
|
||||
g10411/z (u) unmapped_nand2 9 37.8 0 +78 10758 F
|
||||
g10468/in_1 +0 10758
|
||||
g10468/z (u) unmapped_nand2 1 4.5 0 +41 10799 R
|
||||
g10469/in_1 +0 10799
|
||||
g10469/z (u) unmapped_nand2 9 37.8 0 +78 10877 F
|
||||
g10535/in_0 +0 10877
|
||||
g10535/z (u) unmapped_nand2 1 4.5 0 +41 10918 R
|
||||
g10536/in_1 +0 10918
|
||||
g10536/z (u) unmapped_nand2 1 4.2 0 +41 10958 F
|
||||
g10538/in_0 +0 10958
|
||||
g10538/z (u) unmapped_nand2 3 13.5 0 +58 11016 R
|
||||
g135/in_0 +0 11016
|
||||
g135/z (u) unmapped_not 1 4.2 0 +32 11048 F
|
||||
g136/in_0 +0 11048
|
||||
g136/z (u) unmapped_and2 24 100.8 0 +97 11145 F
|
||||
g11043/sel2 +0 11145
|
||||
g11043/z (u) unmapped_mux8 7 29.4 0 +139 11284 F
|
||||
g11497/in_0 +0 11284
|
||||
g11497/z (u) unmapped_nor2 3 13.5 0 +58 11342 R
|
||||
g11549/in_1 +0 11342
|
||||
g11549/z (u) unmapped_nor2 1 4.2 0 +41 11382 F
|
||||
g11600/in_0 +0 11382
|
||||
g11600/z (u) unmapped_nand2 1 4.5 0 +41 11423 R
|
||||
g11601/in_1 +0 11423
|
||||
g11601/z (u) unmapped_nand2 5 21.0 0 +65 11488 F
|
||||
g11670/in_0 +0 11488
|
||||
g11670/z (u) unmapped_nand2 1 4.5 0 +41 11528 R
|
||||
g11671/in_1 +0 11528
|
||||
g11671/z (u) unmapped_nand2 9 37.8 0 +78 11606 F
|
||||
g11732/in_1 +0 11606
|
||||
g11732/z (u) unmapped_nand2 1 4.5 0 +41 11647 R
|
||||
g11733/in_1 +0 11647
|
||||
g11733/z (u) unmapped_nand2 11 46.2 0 +82 11729 F
|
||||
g11809/in_0 +0 11729
|
||||
g11809/z (u) unmapped_nand2 1 4.5 0 +41 11769 R
|
||||
g11810/in_1 +0 11769
|
||||
g11810/z (u) unmapped_nand2 1 4.2 0 +41 11810 F
|
||||
g11812/in_0 +0 11810
|
||||
g11812/z (u) unmapped_nand2 3 13.5 0 +58 11868 R
|
||||
g147/in_0 +0 11868
|
||||
g147/z (u) unmapped_not 1 4.2 0 +32 11900 F
|
||||
g148/in_0 +0 11900
|
||||
g148/z (u) unmapped_and2 26 109.2 0 +99 11999 F
|
||||
g12337/sel2 +0 11999
|
||||
g12337/z (u) unmapped_mux8 7 29.4 0 +139 12138 F
|
||||
g12810/in_0 +0 12138
|
||||
g12810/z (u) unmapped_nor2 3 13.5 0 +58 12195 R
|
||||
g12866/in_1 +0 12195
|
||||
g12866/z (u) unmapped_nor2 1 4.2 0 +41 12236 F
|
||||
g12920/in_0 +0 12236
|
||||
g12920/z (u) unmapped_nand2 1 4.5 0 +41 12276 R
|
||||
g12921/in_1 +0 12276
|
||||
g12921/z (u) unmapped_nand2 5 21.0 0 +65 12341 F
|
||||
g12994/in_0 +0 12341
|
||||
g12994/z (u) unmapped_nand2 1 4.5 0 +41 12382 R
|
||||
g12995/in_1 +0 12382
|
||||
g12995/z (u) unmapped_nand2 9 37.8 0 +78 12460 F
|
||||
g13056/in_1 +0 12460
|
||||
g13056/z (u) unmapped_nand2 1 4.5 0 +41 12500 R
|
||||
g13057/in_1 +0 12500
|
||||
g13057/z (u) unmapped_nand2 13 54.6 0 +85 12585 F
|
||||
g13135/in_0 +0 12585
|
||||
g13135/z (u) unmapped_nand2 1 4.5 0 +41 12626 R
|
||||
g13136/in_1 +0 12626
|
||||
g13136/z (u) unmapped_nand2 1 4.2 0 +41 12667 F
|
||||
g13138/in_0 +0 12667
|
||||
g13138/z (u) unmapped_nand2 3 13.5 0 +58 12724 R
|
||||
g159/in_0 +0 12724
|
||||
g159/z (u) unmapped_not 1 4.2 0 +32 12756 F
|
||||
g160/in_0 +0 12756
|
||||
g160/z (u) unmapped_and2 28 117.6 0 +101 12857 F
|
||||
g13684/sel2 +0 12857
|
||||
g13684/z (u) unmapped_mux8 7 29.4 0 +139 12996 F
|
||||
g14185/in_0 +0 12996
|
||||
g14185/z (u) unmapped_nor2 3 13.5 0 +58 13054 R
|
||||
g14245/in_1 +0 13054
|
||||
g14245/z (u) unmapped_nor2 1 4.2 0 +41 13094 F
|
||||
g14302/in_0 +0 13094
|
||||
g14302/z (u) unmapped_nand2 1 4.5 0 +41 13135 R
|
||||
g14303/in_1 +0 13135
|
||||
g14303/z (u) unmapped_nand2 5 21.0 0 +65 13200 F
|
||||
g14379/in_0 +0 13200
|
||||
g14379/z (u) unmapped_nand2 1 4.5 0 +41 13240 R
|
||||
g14380/in_1 +0 13240
|
||||
g14380/z (u) unmapped_nand2 9 37.8 0 +78 13318 F
|
||||
g14447/in_1 +0 13318
|
||||
g14447/z (u) unmapped_nand2 1 4.5 0 +41 13359 R
|
||||
g14448/in_1 +0 13359
|
||||
g14448/z (u) unmapped_nand2 15 63.0 0 +88 13447 F
|
||||
g14530/in_0 +0 13447
|
||||
g14530/z (u) unmapped_nand2 1 4.5 0 +41 13488 R
|
||||
g14531/in_1 +0 13488
|
||||
g14531/z (u) unmapped_nand2 1 4.2 0 +41 13529 F
|
||||
g14533/in_0 +0 13529
|
||||
g14533/z (u) unmapped_nand2 3 13.5 0 +58 13586 R
|
||||
g171/in_0 +0 13586
|
||||
g171/z (u) unmapped_not 1 4.2 0 +32 13618 F
|
||||
g172/in_0 +0 13618
|
||||
g172/z (u) unmapped_and2 30 126.0 0 +103 13721 F
|
||||
g15107/sel2 +0 13721
|
||||
g15107/z (u) unmapped_mux8 6 25.2 0 +135 13856 F
|
||||
g15640/in_0 +0 13856
|
||||
g15640/z (u) unmapped_nor2 2 9.0 0 +51 13906 R
|
||||
g15704/in_1 +0 13906
|
||||
g15704/z (u) unmapped_nor2 2 8.4 0 +51 13957 F
|
||||
g15767/in_1 +0 13957
|
||||
g15767/z (u) unmapped_nand2 1 4.5 0 +41 13998 R
|
||||
g15836/in_0 +0 13998
|
||||
g15836/z (u) unmapped_not 1 4.2 0 +32 14030 F
|
||||
g15837/in_1 +0 14030
|
||||
g15837/z (u) unmapped_nand2 1 4.5 0 +41 14070 R
|
||||
g15838/in_1 +0 14070
|
||||
g15838/z (u) unmapped_nand2 1 4.2 0 +41 14111 F
|
||||
g15907/in_1 +0 14111
|
||||
g15907/z (u) unmapped_nand2 1 4.5 0 +41 14152 R
|
||||
g15908/in_1 +0 14152
|
||||
g15908/z (u) unmapped_nand2 1 4.2 0 +41 14193 F
|
||||
g15990/in_0 +0 14193
|
||||
g15990/z (u) unmapped_nand2 1 4.5 0 +41 14233 R
|
||||
g15991/in_1 +0 14233
|
||||
g15991/z (u) unmapped_nand2 1 4.2 0 +41 14274 F
|
||||
g15993/in_0 +0 14274
|
||||
g15993/z (u) unmapped_nand2 2 9.0 0 +51 14325 R
|
||||
g186/in_0 +0 14325
|
||||
g186/z (u) unmapped_and2 1 4.5 0 +41 14365 R
|
||||
g187/in_1 +0 14365
|
||||
g187/z (u) unmapped_or2 1 4.5 0 +41 14406 R
|
||||
Alu_3_div_202_57/QUOTIENT[0]
|
||||
g57705/data4 +0 14406
|
||||
g57705/z (u) unmapped_mux20 8 36.0 0 +168 14574 R
|
||||
RegisterFiles/io_inputs_3[0]
|
||||
g2841_g2967/data1 +0 14574
|
||||
g2841_g2967/z (u) unmapped_mux12 1 4.5 0 +120 14694 R
|
||||
regs_7_reg[0]/d <<< unmapped_d_flop +0 14694
|
||||
regs_7_reg[0]/clk setup 400 +56 14750 R
|
||||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
||||
(clock clk) capture 10000 R
|
||||
------------------------------------------------------------------------------------------------
|
||||
Timing slack : -4750ps (TIMING VIOLATION)
|
||||
Start-point : topModule/configController_cycleReg_reg[0]/clk
|
||||
End-point : topModule/RegisterFiles/regs_7_reg[0]/d
|
||||
|
||||
(u) : Net has unmapped pin(s).
|
||||
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
create_library_set -name gscl45nm -timing {/home/jxzhang/projects/cocoon/design/lib/gscl45nm.lib}
|
||||
create_rc_corner -name default_rc_corner -preRoute_res {1.0} -preRoute_cap {1.0} -preRoute_clkres {0.0} -preRoute_clkcap {0.0} -postRoute_res {1.0} -postRoute_cap {1.0} -postRoute_xcap {1.0} -postRoute_clkres {0.0} -postRoute_clkcap {0.0}
|
||||
create_delay_corner -name default_delay_corner -library_set {gscl45nm} -rc_corner {default_rc_corner}
|
||||
create_constraint_mode -name common -sdc_files {/home/jxzhang/projects/cocoon/design/gcd/gscl45nm/objects/gcd.sdc}
|
||||
create_analysis_view -name default_view_hold -constraint_mode {common} -delay_corner {default_delay_corner}
|
||||
create_analysis_view -name default_view_setup -constraint_mode {common} -delay_corner {default_delay_corner}
|
||||
set_analysis_view -setup {default_view_setup} -hold {default_view_hold}
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
# ####################################################################
|
||||
|
||||
# Created by Genus(TM) Synthesis Solution 19.12-s121_1 on Mon Aug 10 21:58:44 CST 2020
|
||||
|
||||
# ####################################################################
|
||||
|
||||
set sdc_version 2.0
|
||||
|
||||
set_units -capacitance 1000fF
|
||||
set_units -time 1000ps
|
||||
|
||||
# Set the current design
|
||||
current_design gcd
|
||||
|
||||
create_clock -name "clk" -period 0.1 -waveform {0.0 0.05} [get_ports clk]
|
||||
set_clock_transition 0.4 [get_clocks clk]
|
||||
set_clock_gating_check -setup 0.0
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports resp_rdy]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports reset]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports req_val]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[0]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[1]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[2]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[3]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[4]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[5]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[6]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[7]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[8]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[9]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[10]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[11]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[12]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[13]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[14]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[15]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[16]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[17]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[18]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[19]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[20]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[21]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[22]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[23]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[24]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[25]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[26]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[27]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[28]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[29]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[30]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[31]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports clk]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports resp_val]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[0]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[1]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[2]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[3]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[4]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[5]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[6]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[7]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[8]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[9]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[10]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[11]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[12]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[13]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[14]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[15]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports req_rdy]
|
||||
set_wire_load_mode "enclosed"
|
||||
|
|
@ -0,0 +1,762 @@
|
|||
|
||||
// Generated by Cadence Genus(TM) Synthesis Solution 19.12-s121_1
|
||||
// Generated on: Aug 10 2020 21:58:44 CST (Aug 10 2020 13:58:44 UTC)
|
||||
|
||||
// Verification Directory fv/gcd
|
||||
|
||||
module RegRst_0x9f365fdf6c8998a(clk, in_, out, reset);
|
||||
input [0:0] clk, reset;
|
||||
input [1:0] in_;
|
||||
output [1:0] out;
|
||||
wire [0:0] clk, reset;
|
||||
wire [1:0] in_;
|
||||
wire [1:0] out;
|
||||
wire n_19, n_22;
|
||||
CDN_flop \out_reg[0] (.clk (clk), .d (n_19), .sena (1'b1), .aclr
|
||||
(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[0]));
|
||||
CDN_flop \out_reg[1] (.clk (clk), .d (n_22), .sena (1'b1), .aclr
|
||||
(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[1]));
|
||||
and g9 (n_19, in_[0], wc);
|
||||
not gc (wc, reset);
|
||||
and g10 (n_22, in_[1], wc0);
|
||||
not gc0 (wc0, reset);
|
||||
endmodule
|
||||
|
||||
module lt_unsigned_rtlopto_model_20(A, B, Z);
|
||||
input [15:0] A, B;
|
||||
output Z;
|
||||
wire [15:0] A, B;
|
||||
wire Z;
|
||||
wire n_68, n_71, n_72, n_74, n_75, n_76, n_77, n_78;
|
||||
wire n_79, n_81, n_82, n_83, n_84, n_85, n_87, n_88;
|
||||
wire n_89, n_90, n_91, n_93, n_94, n_95, n_96, n_97;
|
||||
wire n_99, n_100, n_101, n_102, n_103, n_105, n_106, n_107;
|
||||
wire n_108, n_109, n_111, n_112, n_113, n_114, n_115, n_117;
|
||||
wire n_118, n_121, n_122, n_123, n_124, n_127, n_129, n_131;
|
||||
wire n_132, n_134, n_137, n_139, n_141, n_142, n_144, n_147;
|
||||
wire n_149, n_151, n_152, n_154, n_162, n_164, n_165, n_166;
|
||||
wire n_169, n_177, n_178, n_179, n_181, n_200, n_201, n_202;
|
||||
not g18 (Z, n_68);
|
||||
nand g55 (n_118, n_74, n_75);
|
||||
nor g56 (n_79, n_76, n_77);
|
||||
nor g59 (n_121, n_81, n_77);
|
||||
nor g60 (n_85, n_82, n_83);
|
||||
nor g63 (n_127, n_87, n_83);
|
||||
nor g64 (n_91, n_88, n_89);
|
||||
nor g67 (n_129, n_93, n_89);
|
||||
nor g68 (n_97, n_94, n_95);
|
||||
nor g71 (n_137, n_99, n_95);
|
||||
nor g72 (n_103, n_100, n_101);
|
||||
nor g75 (n_139, n_105, n_101);
|
||||
nor g76 (n_109, n_106, n_107);
|
||||
nor g79 (n_147, n_111, n_107);
|
||||
nor g80 (n_115, n_112, n_113);
|
||||
nor g83 (n_149, n_117, n_113);
|
||||
nand g87 (n_123, n_121, n_118);
|
||||
nand g88 (n_154, n_122, n_123);
|
||||
nand g98 (n_162, n_127, n_129);
|
||||
nand g108 (n_169, n_137, n_139);
|
||||
nand g118 (n_177, n_147, n_149);
|
||||
nand g129 (n_181, n_164, n_165);
|
||||
nor g143 (n_179, n_177, n_166);
|
||||
nor g146 (n_200, n_169, n_177);
|
||||
nand g164 (n_202, n_200, n_181);
|
||||
nand g165 (n_68, n_201, n_202);
|
||||
and g207 (n_111, B[12], wc1);
|
||||
not gc1 (wc1, A[12]);
|
||||
and g208 (n_107, B[13], wc2);
|
||||
not gc2 (wc2, A[13]);
|
||||
and g209 (n_117, B[14], wc3);
|
||||
not gc3 (wc3, A[14]);
|
||||
and g210 (n_113, B[15], wc4);
|
||||
not gc4 (wc4, A[15]);
|
||||
or g211 (n_94, B[8], wc5);
|
||||
not gc5 (wc5, A[8]);
|
||||
and g212 (n_95, B[9], wc6);
|
||||
not gc6 (wc6, A[9]);
|
||||
or g213 (n_96, B[9], wc7);
|
||||
not gc7 (wc7, A[9]);
|
||||
and g214 (n_105, B[10], wc8);
|
||||
not gc8 (wc8, A[10]);
|
||||
and g215 (n_101, B[11], wc9);
|
||||
not gc9 (wc9, A[11]);
|
||||
or g216 (n_100, B[10], wc10);
|
||||
not gc10 (wc10, A[10]);
|
||||
or g217 (n_102, B[11], wc11);
|
||||
not gc11 (wc11, A[11]);
|
||||
or g218 (n_106, B[12], wc12);
|
||||
not gc12 (wc12, A[12]);
|
||||
or g219 (n_108, B[13], wc13);
|
||||
not gc13 (wc13, A[13]);
|
||||
or g220 (n_112, B[14], wc14);
|
||||
not gc14 (wc14, A[14]);
|
||||
or g221 (n_114, B[15], wc15);
|
||||
not gc15 (wc15, A[15]);
|
||||
and g222 (n_99, B[8], wc16);
|
||||
not gc16 (wc16, A[8]);
|
||||
or g223 (n_82, B[4], wc17);
|
||||
not gc17 (wc17, A[4]);
|
||||
and g224 (n_83, B[5], wc18);
|
||||
not gc18 (wc18, A[5]);
|
||||
or g225 (n_84, B[5], wc19);
|
||||
not gc19 (wc19, A[5]);
|
||||
and g226 (n_93, B[6], wc20);
|
||||
not gc20 (wc20, A[6]);
|
||||
and g227 (n_89, B[7], wc21);
|
||||
not gc21 (wc21, A[7]);
|
||||
or g228 (n_88, B[6], wc22);
|
||||
not gc22 (wc22, A[6]);
|
||||
or g229 (n_90, B[7], wc23);
|
||||
not gc23 (wc23, A[7]);
|
||||
or g230 (n_76, B[2], wc24);
|
||||
not gc24 (wc24, A[2]);
|
||||
and g231 (n_77, B[3], wc25);
|
||||
not gc25 (wc25, A[3]);
|
||||
or g232 (n_78, B[3], wc26);
|
||||
not gc26 (wc26, A[3]);
|
||||
and g233 (n_81, B[2], wc27);
|
||||
not gc27 (wc27, A[2]);
|
||||
or g234 (n_74, B[1], wc28);
|
||||
not gc28 (wc28, A[1]);
|
||||
or g235 (n_72, wc29, A[0]);
|
||||
not gc29 (wc29, B[0]);
|
||||
and g236 (n_71, B[1], wc30);
|
||||
not gc30 (wc30, A[1]);
|
||||
and g237 (n_87, B[4], wc31);
|
||||
not gc31 (wc31, A[4]);
|
||||
and g238 (n_134, n_96, wc32);
|
||||
not gc32 (wc32, n_97);
|
||||
and g239 (n_141, n_102, wc33);
|
||||
not gc33 (wc33, n_103);
|
||||
and g240 (n_144, n_108, wc34);
|
||||
not gc34 (wc34, n_109);
|
||||
and g241 (n_151, n_114, wc35);
|
||||
not gc35 (wc35, n_115);
|
||||
and g242 (n_124, n_84, wc36);
|
||||
not gc36 (wc36, n_85);
|
||||
and g243 (n_131, n_90, wc37);
|
||||
not gc37 (wc37, n_91);
|
||||
and g244 (n_122, n_78, wc38);
|
||||
not gc38 (wc38, n_79);
|
||||
or g245 (n_75, n_71, wc39);
|
||||
not gc39 (wc39, n_72);
|
||||
and g246 (n_142, wc40, n_139);
|
||||
not gc40 (wc40, n_134);
|
||||
and g247 (n_152, wc41, n_149);
|
||||
not gc41 (wc41, n_144);
|
||||
and g248 (n_132, wc42, n_129);
|
||||
not gc42 (wc42, n_124);
|
||||
and g249 (n_166, wc43, n_141);
|
||||
not gc43 (wc43, n_142);
|
||||
and g250 (n_178, wc44, n_151);
|
||||
not gc44 (wc44, n_152);
|
||||
and g251 (n_164, wc45, n_131);
|
||||
not gc45 (wc45, n_132);
|
||||
and g252 (n_201, n_178, wc46);
|
||||
not gc46 (wc46, n_179);
|
||||
or g253 (n_165, n_162, wc47);
|
||||
not gc47 (wc47, n_154);
|
||||
endmodule
|
||||
|
||||
module RegEn_0x68db79c4ec1d6e5b(clk, en, in_, out, reset);
|
||||
input [0:0] clk, en, reset;
|
||||
input [15:0] in_;
|
||||
output [15:0] out;
|
||||
wire [0:0] clk, en, reset;
|
||||
wire [15:0] in_;
|
||||
wire [15:0] out;
|
||||
wire n_98, n_99, n_101, n_103, n_105, n_107, n_109, n_111;
|
||||
wire n_113, n_115, n_117, n_119, n_121, n_123, n_125, n_127;
|
||||
wire n_129;
|
||||
CDN_flop \out_reg[0] (.clk (clk), .d (n_99), .sena (1'b1), .aclr
|
||||
(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[0]));
|
||||
CDN_flop \out_reg[1] (.clk (clk), .d (n_101), .sena (1'b1), .aclr
|
||||
(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[1]));
|
||||
CDN_flop \out_reg[2] (.clk (clk), .d (n_103), .sena (1'b1), .aclr
|
||||
(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[2]));
|
||||
CDN_flop \out_reg[3] (.clk (clk), .d (n_105), .sena (1'b1), .aclr
|
||||
(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[3]));
|
||||
CDN_flop \out_reg[4] (.clk (clk), .d (n_107), .sena (1'b1), .aclr
|
||||
(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[4]));
|
||||
CDN_flop \out_reg[5] (.clk (clk), .d (n_109), .sena (1'b1), .aclr
|
||||
(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[5]));
|
||||
CDN_flop \out_reg[6] (.clk (clk), .d (n_111), .sena (1'b1), .aclr
|
||||
(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[6]));
|
||||
CDN_flop \out_reg[7] (.clk (clk), .d (n_113), .sena (1'b1), .aclr
|
||||
(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[7]));
|
||||
CDN_flop \out_reg[8] (.clk (clk), .d (n_115), .sena (1'b1), .aclr
|
||||
(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[8]));
|
||||
CDN_flop \out_reg[9] (.clk (clk), .d (n_117), .sena (1'b1), .aclr
|
||||
(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[9]));
|
||||
CDN_flop \out_reg[10] (.clk (clk), .d (n_119), .sena (1'b1), .aclr
|
||||
(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[10]));
|
||||
CDN_flop \out_reg[11] (.clk (clk), .d (n_121), .sena (1'b1), .aclr
|
||||
(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[11]));
|
||||
CDN_flop \out_reg[12] (.clk (clk), .d (n_123), .sena (1'b1), .aclr
|
||||
(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[12]));
|
||||
CDN_flop \out_reg[13] (.clk (clk), .d (n_125), .sena (1'b1), .aclr
|
||||
(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[13]));
|
||||
CDN_flop \out_reg[14] (.clk (clk), .d (n_127), .sena (1'b1), .aclr
|
||||
(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[14]));
|
||||
CDN_flop \out_reg[15] (.clk (clk), .d (n_129), .sena (1'b1), .aclr
|
||||
(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[15]));
|
||||
not g18 (n_98, en);
|
||||
CDN_mux2 g19_g1(.sel0 (n_98), .data0 (out[0]), .sel1 (en), .data1
|
||||
(in_[0]), .z (n_99));
|
||||
CDN_mux2 g21_g1(.sel0 (n_98), .data0 (out[1]), .sel1 (en), .data1
|
||||
(in_[1]), .z (n_101));
|
||||
CDN_mux2 g23_g1(.sel0 (n_98), .data0 (out[2]), .sel1 (en), .data1
|
||||
(in_[2]), .z (n_103));
|
||||
CDN_mux2 g25_g1(.sel0 (n_98), .data0 (out[3]), .sel1 (en), .data1
|
||||
(in_[3]), .z (n_105));
|
||||
CDN_mux2 g27_g1(.sel0 (n_98), .data0 (out[4]), .sel1 (en), .data1
|
||||
(in_[4]), .z (n_107));
|
||||
CDN_mux2 g29_g1(.sel0 (n_98), .data0 (out[5]), .sel1 (en), .data1
|
||||
(in_[5]), .z (n_109));
|
||||
CDN_mux2 g31_g1(.sel0 (n_98), .data0 (out[6]), .sel1 (en), .data1
|
||||
(in_[6]), .z (n_111));
|
||||
CDN_mux2 g33_g1(.sel0 (n_98), .data0 (out[7]), .sel1 (en), .data1
|
||||
(in_[7]), .z (n_113));
|
||||
CDN_mux2 g35_g1(.sel0 (n_98), .data0 (out[8]), .sel1 (en), .data1
|
||||
(in_[8]), .z (n_115));
|
||||
CDN_mux2 g37_g1(.sel0 (n_98), .data0 (out[9]), .sel1 (en), .data1
|
||||
(in_[9]), .z (n_117));
|
||||
CDN_mux2 g39_g1(.sel0 (n_98), .data0 (out[10]), .sel1 (en), .data1
|
||||
(in_[10]), .z (n_119));
|
||||
CDN_mux2 g41_g1(.sel0 (n_98), .data0 (out[11]), .sel1 (en), .data1
|
||||
(in_[11]), .z (n_121));
|
||||
CDN_mux2 g43_g1(.sel0 (n_98), .data0 (out[12]), .sel1 (en), .data1
|
||||
(in_[12]), .z (n_123));
|
||||
CDN_mux2 g45_g1(.sel0 (n_98), .data0 (out[13]), .sel1 (en), .data1
|
||||
(in_[13]), .z (n_125));
|
||||
CDN_mux2 g47_g1(.sel0 (n_98), .data0 (out[14]), .sel1 (en), .data1
|
||||
(in_[14]), .z (n_127));
|
||||
CDN_mux2 g49_g1(.sel0 (n_98), .data0 (out[15]), .sel1 (en), .data1
|
||||
(in_[15]), .z (n_129));
|
||||
endmodule
|
||||
|
||||
module Mux_0xdd6473406d1a99a(clk, in_$000, in_$001, out, reset, sel);
|
||||
input [0:0] clk, reset, sel;
|
||||
input [15:0] in_$000, in_$001;
|
||||
output [15:0] out;
|
||||
wire [0:0] clk, reset, sel;
|
||||
wire [15:0] in_$000, in_$001;
|
||||
wire [15:0] out;
|
||||
CDN_bmux2 \mux_in_[sel]_721_11_g1 (.sel0 (sel), .data0 (in_$000[15]),
|
||||
.data1 (in_$001[15]), .z (out[15]));
|
||||
CDN_bmux2 \mux_in_[sel]_721_11_g2 (.sel0 (sel), .data0 (in_$000[14]),
|
||||
.data1 (in_$001[14]), .z (out[14]));
|
||||
CDN_bmux2 \mux_in_[sel]_721_11_g3 (.sel0 (sel), .data0 (in_$000[13]),
|
||||
.data1 (in_$001[13]), .z (out[13]));
|
||||
CDN_bmux2 \mux_in_[sel]_721_11_g4 (.sel0 (sel), .data0 (in_$000[12]),
|
||||
.data1 (in_$001[12]), .z (out[12]));
|
||||
CDN_bmux2 \mux_in_[sel]_721_11_g5 (.sel0 (sel), .data0 (in_$000[11]),
|
||||
.data1 (in_$001[11]), .z (out[11]));
|
||||
CDN_bmux2 \mux_in_[sel]_721_11_g6 (.sel0 (sel), .data0 (in_$000[10]),
|
||||
.data1 (in_$001[10]), .z (out[10]));
|
||||
CDN_bmux2 \mux_in_[sel]_721_11_g7 (.sel0 (sel), .data0 (in_$000[9]),
|
||||
.data1 (in_$001[9]), .z (out[9]));
|
||||
CDN_bmux2 \mux_in_[sel]_721_11_g8 (.sel0 (sel), .data0 (in_$000[8]),
|
||||
.data1 (in_$001[8]), .z (out[8]));
|
||||
CDN_bmux2 \mux_in_[sel]_721_11_g9 (.sel0 (sel), .data0 (in_$000[7]),
|
||||
.data1 (in_$001[7]), .z (out[7]));
|
||||
CDN_bmux2 \mux_in_[sel]_721_11_g10 (.sel0 (sel), .data0 (in_$000[6]),
|
||||
.data1 (in_$001[6]), .z (out[6]));
|
||||
CDN_bmux2 \mux_in_[sel]_721_11_g11 (.sel0 (sel), .data0 (in_$000[5]),
|
||||
.data1 (in_$001[5]), .z (out[5]));
|
||||
CDN_bmux2 \mux_in_[sel]_721_11_g12 (.sel0 (sel), .data0 (in_$000[4]),
|
||||
.data1 (in_$001[4]), .z (out[4]));
|
||||
CDN_bmux2 \mux_in_[sel]_721_11_g13 (.sel0 (sel), .data0 (in_$000[3]),
|
||||
.data1 (in_$001[3]), .z (out[3]));
|
||||
CDN_bmux2 \mux_in_[sel]_721_11_g14 (.sel0 (sel), .data0 (in_$000[2]),
|
||||
.data1 (in_$001[2]), .z (out[2]));
|
||||
CDN_bmux2 \mux_in_[sel]_721_11_g15 (.sel0 (sel), .data0 (in_$000[1]),
|
||||
.data1 (in_$001[1]), .z (out[1]));
|
||||
CDN_bmux2 \mux_in_[sel]_721_11_g16 (.sel0 (sel), .data0 (in_$000[0]),
|
||||
.data1 (in_$001[0]), .z (out[0]));
|
||||
endmodule
|
||||
|
||||
module ZeroComparator_0x422b1f52edd46a85(clk, in_, out, reset);
|
||||
input [0:0] clk, reset;
|
||||
input [15:0] in_;
|
||||
output [0:0] out;
|
||||
wire [0:0] clk, reset;
|
||||
wire [15:0] in_;
|
||||
wire [0:0] out;
|
||||
wire n_20, n_21, n_22, n_23, n_24, n_26;
|
||||
xnor g1 (n_26, in_[0], 1'b0);
|
||||
nor g2 (n_20, in_[15], in_[14], in_[13], in_[12]);
|
||||
nor g3 (n_21, in_[11], in_[10], in_[9], in_[8]);
|
||||
nor g4 (n_22, in_[7], in_[6], in_[5], in_[4]);
|
||||
nor g5 (n_23, in_[3], in_[2], in_[1]);
|
||||
nand g6 (n_24, n_26, n_20, n_21, n_22);
|
||||
and g9 (out, wc48, n_23);
|
||||
not gc48 (wc48, n_24);
|
||||
endmodule
|
||||
|
||||
module sub_unsigned(A, B, Z);
|
||||
input [15:0] A, B;
|
||||
output [15:0] Z;
|
||||
wire [15:0] A, B;
|
||||
wire [15:0] Z;
|
||||
wire n_51, n_52, n_53, n_54, n_55, n_56, n_57, n_58;
|
||||
wire n_59, n_60, n_61, n_62, n_63, n_64, n_65, n_66;
|
||||
wire n_69, n_71, n_72, n_73, n_74, n_75, n_76, n_77;
|
||||
wire n_78, n_79, n_80, n_81, n_82, n_83, n_84, n_85;
|
||||
wire n_86, n_87, n_88, n_89, n_90, n_91, n_92, n_93;
|
||||
wire n_94, n_95, n_96, n_97, n_98, n_99, n_100, n_101;
|
||||
wire n_102, n_103, n_104, n_105, n_106, n_107, n_108, n_109;
|
||||
wire n_110, n_111, n_112, n_113, n_114, n_117, n_118, n_119;
|
||||
wire n_120, n_121, n_122, n_123, n_124, n_125, n_126, n_127;
|
||||
wire n_128, n_129, n_130, n_131, n_132, n_133, n_134, n_135;
|
||||
wire n_136, n_137, n_138, n_139, n_140, n_141, n_142, n_143;
|
||||
wire n_144, n_145, n_146, n_147, n_148, n_154, n_155, n_156;
|
||||
wire n_157, n_158, n_159, n_160, n_161, n_162, n_163, n_164;
|
||||
wire n_165, n_166, n_167, n_168, n_169, n_170, n_171, n_172;
|
||||
wire n_173, n_174, n_175, n_176, n_181, n_182, n_183, n_184;
|
||||
wire n_185, n_186, n_187, n_188, n_189, n_190, n_191, n_192;
|
||||
wire n_193, n_194, n_195, n_196, n_197, n_198, n_199, n_203;
|
||||
wire n_204, n_205, n_206, n_207, n_208, n_209, n_210, n_211;
|
||||
wire n_212, n_213, n_214, n_215, n_216, n_217, n_218, n_219;
|
||||
wire n_220, n_221, n_222, n_223, n_224, n_225, n_226, n_227;
|
||||
wire n_228, n_229, n_230, n_231, n_232, n_233, n_234, n_235;
|
||||
wire n_236, n_237;
|
||||
not g2 (n_51, B[15]);
|
||||
not g3 (n_52, B[14]);
|
||||
not g4 (n_53, B[13]);
|
||||
not g5 (n_54, B[12]);
|
||||
not g6 (n_55, B[11]);
|
||||
not g7 (n_56, B[10]);
|
||||
not g8 (n_57, B[9]);
|
||||
not g9 (n_58, B[8]);
|
||||
not g10 (n_59, B[7]);
|
||||
not g11 (n_60, B[6]);
|
||||
not g12 (n_61, B[5]);
|
||||
not g13 (n_62, B[4]);
|
||||
not g14 (n_63, B[3]);
|
||||
not g15 (n_64, B[2]);
|
||||
not g16 (n_65, B[1]);
|
||||
not g17 (n_66, B[0]);
|
||||
xor g19 (n_237, A[0], n_66);
|
||||
nand g22 (n_72, n_69, B[0]);
|
||||
nor g23 (n_71, A[1], n_65);
|
||||
nand g24 (n_74, A[1], n_65);
|
||||
nor g25 (n_81, A[2], n_64);
|
||||
nand g26 (n_76, A[2], n_64);
|
||||
nor g27 (n_77, A[3], n_63);
|
||||
nand g28 (n_78, A[3], n_63);
|
||||
nor g29 (n_87, A[4], n_62);
|
||||
nand g30 (n_82, A[4], n_62);
|
||||
nor g31 (n_83, A[5], n_61);
|
||||
nand g32 (n_84, A[5], n_61);
|
||||
nor g33 (n_93, A[6], n_60);
|
||||
nand g34 (n_88, A[6], n_60);
|
||||
nor g35 (n_89, A[7], n_59);
|
||||
nand g36 (n_90, A[7], n_59);
|
||||
nor g37 (n_99, A[8], n_58);
|
||||
nand g38 (n_94, A[8], n_58);
|
||||
nor g39 (n_95, A[9], n_57);
|
||||
nand g40 (n_96, A[9], n_57);
|
||||
nor g41 (n_105, A[10], n_56);
|
||||
nand g42 (n_100, A[10], n_56);
|
||||
nor g43 (n_101, A[11], n_55);
|
||||
nand g44 (n_102, A[11], n_55);
|
||||
nor g45 (n_111, A[12], n_54);
|
||||
nand g46 (n_106, A[12], n_54);
|
||||
nor g47 (n_107, A[13], n_53);
|
||||
nand g48 (n_108, A[13], n_53);
|
||||
nor g49 (n_117, A[14], n_52);
|
||||
nand g50 (n_112, A[14], n_52);
|
||||
nor g51 (n_113, A[15], n_51);
|
||||
nand g52 (n_114, A[15], n_51);
|
||||
not g53 (n_73, n_71);
|
||||
nand g54 (n_75, n_72, n_73);
|
||||
nand g55 (n_118, n_74, n_75);
|
||||
nor g56 (n_79, n_76, n_77);
|
||||
not g57 (n_80, n_78);
|
||||
nor g58 (n_122, n_79, n_80);
|
||||
nor g59 (n_121, n_81, n_77);
|
||||
nor g60 (n_85, n_82, n_83);
|
||||
not g61 (n_86, n_84);
|
||||
nor g62 (n_124, n_85, n_86);
|
||||
nor g63 (n_127, n_87, n_83);
|
||||
nor g64 (n_91, n_88, n_89);
|
||||
not g65 (n_92, n_90);
|
||||
nor g66 (n_131, n_91, n_92);
|
||||
nor g67 (n_129, n_93, n_89);
|
||||
nor g68 (n_97, n_94, n_95);
|
||||
not g69 (n_98, n_96);
|
||||
nor g70 (n_134, n_97, n_98);
|
||||
nor g71 (n_137, n_99, n_95);
|
||||
nor g72 (n_103, n_100, n_101);
|
||||
not g73 (n_104, n_102);
|
||||
nor g74 (n_141, n_103, n_104);
|
||||
nor g75 (n_139, n_105, n_101);
|
||||
nor g76 (n_109, n_106, n_107);
|
||||
not g77 (n_110, n_108);
|
||||
nor g78 (n_144, n_109, n_110);
|
||||
nor g79 (n_147, n_111, n_107);
|
||||
not g84 (n_119, n_81);
|
||||
nand g85 (n_120, n_118, n_119);
|
||||
nand g86 (n_206, n_76, n_120);
|
||||
nand g87 (n_123, n_121, n_118);
|
||||
nand g88 (n_154, n_122, n_123);
|
||||
nor g89 (n_125, n_93, n_124);
|
||||
not g90 (n_126, n_88);
|
||||
nor g91 (n_160, n_125, n_126);
|
||||
not g92 (n_128, n_93);
|
||||
nand g93 (n_158, n_127, n_128);
|
||||
not g94 (n_130, n_129);
|
||||
nor g95 (n_132, n_124, n_130);
|
||||
not g96 (n_133, n_131);
|
||||
nor g97 (n_164, n_132, n_133);
|
||||
nand g98 (n_162, n_127, n_129);
|
||||
nor g99 (n_135, n_105, n_134);
|
||||
not g100 (n_136, n_100);
|
||||
nor g101 (n_187, n_135, n_136);
|
||||
not g102 (n_138, n_105);
|
||||
nand g103 (n_185, n_137, n_138);
|
||||
not g104 (n_140, n_139);
|
||||
nor g105 (n_142, n_134, n_140);
|
||||
not g106 (n_143, n_141);
|
||||
nor g107 (n_166, n_142, n_143);
|
||||
nand g108 (n_169, n_137, n_139);
|
||||
nor g109 (n_145, n_117, n_144);
|
||||
not g110 (n_146, n_112);
|
||||
nor g111 (n_174, n_145, n_146);
|
||||
not g112 (n_148, n_117);
|
||||
nand g113 (n_173, n_147, n_148);
|
||||
not g119 (n_155, n_87);
|
||||
nand g120 (n_156, n_154, n_155);
|
||||
nand g121 (n_210, n_82, n_156);
|
||||
nand g122 (n_157, n_127, n_154);
|
||||
nand g123 (n_212, n_124, n_157);
|
||||
not g124 (n_159, n_158);
|
||||
nand g125 (n_161, n_154, n_159);
|
||||
nand g126 (n_215, n_160, n_161);
|
||||
not g127 (n_163, n_162);
|
||||
nand g128 (n_165, n_154, n_163);
|
||||
nand g129 (n_181, n_164, n_165);
|
||||
nor g130 (n_167, n_111, n_166);
|
||||
not g131 (n_168, n_106);
|
||||
nor g132 (n_192, n_167, n_168);
|
||||
nor g133 (n_191, n_111, n_169);
|
||||
not g134 (n_170, n_147);
|
||||
nor g135 (n_171, n_166, n_170);
|
||||
not g136 (n_172, n_144);
|
||||
nor g137 (n_195, n_171, n_172);
|
||||
nor g138 (n_194, n_169, n_170);
|
||||
nor g139 (n_175, n_173, n_166);
|
||||
not g140 (n_176, n_174);
|
||||
nor g141 (n_198, n_175, n_176);
|
||||
nor g142 (n_197, n_169, n_173);
|
||||
not g147 (n_182, n_99);
|
||||
nand g148 (n_183, n_181, n_182);
|
||||
nand g149 (n_219, n_94, n_183);
|
||||
nand g150 (n_184, n_137, n_181);
|
||||
nand g151 (n_221, n_134, n_184);
|
||||
not g152 (n_186, n_185);
|
||||
nand g153 (n_188, n_181, n_186);
|
||||
nand g154 (n_224, n_187, n_188);
|
||||
not g155 (n_189, n_169);
|
||||
nand g156 (n_190, n_181, n_189);
|
||||
nand g157 (n_227, n_166, n_190);
|
||||
nand g158 (n_193, n_191, n_181);
|
||||
nand g159 (n_230, n_192, n_193);
|
||||
nand g160 (n_196, n_194, n_181);
|
||||
nand g161 (n_232, n_195, n_196);
|
||||
nand g162 (n_199, n_197, n_181);
|
||||
nand g163 (n_235, n_198, n_199);
|
||||
nand g166 (n_203, n_73, n_74);
|
||||
xnor g167 (Z[1], n_72, n_203);
|
||||
nand g168 (n_204, n_119, n_76);
|
||||
xnor g169 (Z[2], n_118, n_204);
|
||||
not g170 (n_205, n_77);
|
||||
nand g171 (n_207, n_205, n_78);
|
||||
xnor g172 (Z[3], n_206, n_207);
|
||||
nand g173 (n_208, n_155, n_82);
|
||||
xnor g174 (Z[4], n_154, n_208);
|
||||
not g175 (n_209, n_83);
|
||||
nand g176 (n_211, n_209, n_84);
|
||||
xnor g177 (Z[5], n_210, n_211);
|
||||
nand g178 (n_213, n_128, n_88);
|
||||
xnor g179 (Z[6], n_212, n_213);
|
||||
not g180 (n_214, n_89);
|
||||
nand g181 (n_216, n_214, n_90);
|
||||
xnor g182 (Z[7], n_215, n_216);
|
||||
nand g183 (n_217, n_182, n_94);
|
||||
xnor g184 (Z[8], n_181, n_217);
|
||||
not g185 (n_218, n_95);
|
||||
nand g186 (n_220, n_218, n_96);
|
||||
xnor g187 (Z[9], n_219, n_220);
|
||||
nand g188 (n_222, n_138, n_100);
|
||||
xnor g189 (Z[10], n_221, n_222);
|
||||
not g190 (n_223, n_101);
|
||||
nand g191 (n_225, n_223, n_102);
|
||||
xnor g192 (Z[11], n_224, n_225);
|
||||
not g193 (n_226, n_111);
|
||||
nand g194 (n_228, n_226, n_106);
|
||||
xnor g195 (Z[12], n_227, n_228);
|
||||
not g196 (n_229, n_107);
|
||||
nand g197 (n_231, n_229, n_108);
|
||||
xnor g198 (Z[13], n_230, n_231);
|
||||
nand g199 (n_233, n_148, n_112);
|
||||
xnor g200 (Z[14], n_232, n_233);
|
||||
not g201 (n_234, n_113);
|
||||
nand g202 (n_236, n_234, n_114);
|
||||
xnor g203 (Z[15], n_235, n_236);
|
||||
not g205 (n_69, A[0]);
|
||||
not g206 (Z[0], n_237);
|
||||
endmodule
|
||||
|
||||
module gcd(clk, req_msg, req_rdy, req_val, reset, resp_msg, resp_rdy,
|
||||
resp_val);
|
||||
input clk, req_val, reset, resp_rdy;
|
||||
input [31:0] req_msg;
|
||||
output req_rdy, resp_val;
|
||||
output [15:0] resp_msg;
|
||||
wire clk, req_val, reset, resp_rdy;
|
||||
wire [31:0] req_msg;
|
||||
wire req_rdy, resp_val;
|
||||
wire [15:0] resp_msg;
|
||||
wire [1:0] ctrl_state$in_;
|
||||
wire [1:0] ctrl_state$out;
|
||||
wire [15:0] dpath_a_reg$out;
|
||||
wire [15:0] dpath_b_reg$out;
|
||||
wire [0:0] ctrl$a_reg_en;
|
||||
wire [15:0] dpath_a_mux$out;
|
||||
wire [15:0] dpath_b_mux$out;
|
||||
wire [0:0] ctrl$b_reg_en;
|
||||
wire [0:0] dpath$is_b_zero;
|
||||
wire n_2, n_7, n_39, n_45, n_51, n_57, n_63, n_69;
|
||||
wire n_75, n_81, n_87, n_93, n_94, n_99, n_102, n_103;
|
||||
wire n_105, n_108, n_109, n_110, n_111, n_112, n_476, n_477;
|
||||
wire n_478, n_479, n_480, n_481, n_482, n_483, n_484, n_485;
|
||||
RegRst_0x9f365fdf6c8998a ctrl_state(.clk (clk), .in_
|
||||
(ctrl_state$in_), .out (ctrl_state$out), .reset (reset));
|
||||
lt_unsigned_rtlopto_model_20 dpath_a_lt_b_lt_607_16(.A
|
||||
(dpath_a_reg$out), .B (dpath_b_reg$out), .Z (n_94));
|
||||
RegEn_0x68db79c4ec1d6e5b dpath_a_reg(.clk (clk), .en (ctrl$a_reg_en),
|
||||
.in_ (dpath_a_mux$out), .out (dpath_a_reg$out), .reset (1'b0));
|
||||
Mux_0xdd6473406d1a99a dpath_b_mux(.clk (1'b0), .in_$000
|
||||
(dpath_a_reg$out), .in_$001 (req_msg[15:0]), .out
|
||||
(dpath_b_mux$out), .reset (1'b0), .sel (req_rdy));
|
||||
RegEn_0x68db79c4ec1d6e5b dpath_b_reg(.clk (clk), .en (ctrl$b_reg_en),
|
||||
.in_ (dpath_b_mux$out), .out (dpath_b_reg$out), .reset (1'b0));
|
||||
ZeroComparator_0x422b1f52edd46a85 dpath_b_zero(.clk (1'b0), .in_
|
||||
(dpath_b_reg$out), .out (dpath$is_b_zero), .reset (1'b0));
|
||||
sub_unsigned dpath_sub_sub_752_15(.A (dpath_a_reg$out), .B
|
||||
(dpath_b_reg$out), .Z (resp_msg));
|
||||
CDN_bmux4 ctrl_mux_b_reg_en_279_10_g1(.sel0 (ctrl_state$out[0]),
|
||||
.data0 (1'b1), .data1 (n_94), .sel1 (ctrl_state$out[1]), .data2
|
||||
(1'b0), .data3 (1'b0), .z (ctrl$b_reg_en));
|
||||
not g4 (ctrl$a_reg_en[0], ctrl_state$out[1]);
|
||||
nor g22 (req_rdy, ctrl_state$out[0], ctrl_state$out[1]);
|
||||
nor g219 (resp_val, ctrl$a_reg_en[0], ctrl_state$out[0]);
|
||||
not g1 (n_2, ctrl_state$out[0]);
|
||||
or g2 (n_7, n_2, ctrl_state$out[1]);
|
||||
CDN_bmux2 g3(.sel0 (n_94), .data0 (n_476), .data1 (n_477), .z
|
||||
(dpath_a_mux$out[0]));
|
||||
CDN_bmux2 g6(.sel0 (n_94), .data0 (n_478), .data1 (n_479), .z
|
||||
(dpath_a_mux$out[1]));
|
||||
CDN_bmux2 g9(.sel0 (n_94), .data0 (n_480), .data1 (n_481), .z
|
||||
(dpath_a_mux$out[2]));
|
||||
CDN_bmux2 g12(.sel0 (n_94), .data0 (n_482), .data1 (n_483), .z
|
||||
(dpath_a_mux$out[3]));
|
||||
CDN_bmux2 g15(.sel0 (n_94), .data0 (n_484), .data1 (n_485), .z
|
||||
(dpath_a_mux$out[4]));
|
||||
CDN_bmux2 g18(.sel0 (n_94), .data0 (resp_msg[5]), .data1
|
||||
(dpath_b_reg$out[5]), .z (n_39));
|
||||
CDN_bmux2 g19(.sel0 (n_7), .data0 (n_39), .data1 (req_msg[21]), .z
|
||||
(dpath_a_mux$out[5]));
|
||||
CDN_bmux2 g21(.sel0 (n_94), .data0 (resp_msg[6]), .data1
|
||||
(dpath_b_reg$out[6]), .z (n_45));
|
||||
CDN_bmux2 g221(.sel0 (n_7), .data0 (n_45), .data1 (req_msg[22]), .z
|
||||
(dpath_a_mux$out[6]));
|
||||
CDN_bmux2 g24(.sel0 (n_94), .data0 (resp_msg[7]), .data1
|
||||
(dpath_b_reg$out[7]), .z (n_51));
|
||||
CDN_bmux2 g25(.sel0 (n_7), .data0 (n_51), .data1 (req_msg[23]), .z
|
||||
(dpath_a_mux$out[7]));
|
||||
CDN_bmux2 g27(.sel0 (n_94), .data0 (resp_msg[8]), .data1
|
||||
(dpath_b_reg$out[8]), .z (n_57));
|
||||
CDN_bmux2 g28(.sel0 (n_7), .data0 (n_57), .data1 (req_msg[24]), .z
|
||||
(dpath_a_mux$out[8]));
|
||||
CDN_bmux2 g30(.sel0 (n_94), .data0 (resp_msg[9]), .data1
|
||||
(dpath_b_reg$out[9]), .z (n_63));
|
||||
CDN_bmux2 g31(.sel0 (n_7), .data0 (n_63), .data1 (req_msg[25]), .z
|
||||
(dpath_a_mux$out[9]));
|
||||
CDN_bmux2 g33(.sel0 (n_94), .data0 (resp_msg[10]), .data1
|
||||
(dpath_b_reg$out[10]), .z (n_69));
|
||||
CDN_bmux2 g34(.sel0 (n_7), .data0 (n_69), .data1 (req_msg[26]), .z
|
||||
(dpath_a_mux$out[10]));
|
||||
CDN_bmux2 g36(.sel0 (n_94), .data0 (resp_msg[11]), .data1
|
||||
(dpath_b_reg$out[11]), .z (n_75));
|
||||
CDN_bmux2 g37(.sel0 (n_7), .data0 (n_75), .data1 (req_msg[27]), .z
|
||||
(dpath_a_mux$out[11]));
|
||||
CDN_bmux2 g39(.sel0 (n_94), .data0 (resp_msg[12]), .data1
|
||||
(dpath_b_reg$out[12]), .z (n_81));
|
||||
CDN_bmux2 g40(.sel0 (n_7), .data0 (n_81), .data1 (req_msg[28]), .z
|
||||
(dpath_a_mux$out[12]));
|
||||
CDN_bmux2 g42(.sel0 (n_94), .data0 (resp_msg[13]), .data1
|
||||
(dpath_b_reg$out[13]), .z (n_87));
|
||||
CDN_bmux2 g43(.sel0 (n_7), .data0 (n_87), .data1 (req_msg[29]), .z
|
||||
(dpath_a_mux$out[13]));
|
||||
CDN_bmux2 g45(.sel0 (n_94), .data0 (resp_msg[14]), .data1
|
||||
(dpath_b_reg$out[14]), .z (n_93));
|
||||
CDN_bmux2 g46(.sel0 (n_7), .data0 (n_93), .data1 (req_msg[30]), .z
|
||||
(dpath_a_mux$out[14]));
|
||||
CDN_bmux2 g48(.sel0 (n_94), .data0 (resp_msg[15]), .data1
|
||||
(dpath_b_reg$out[15]), .z (n_99));
|
||||
CDN_bmux2 g49(.sel0 (n_7), .data0 (n_99), .data1 (req_msg[31]), .z
|
||||
(dpath_a_mux$out[15]));
|
||||
not g50 (n_102, dpath$is_b_zero[0]);
|
||||
or g51 (n_103, n_102, n_94);
|
||||
CDN_bmux2 g52(.sel0 (ctrl_state$out[0]), .data0 (req_val), .data1
|
||||
(n_103), .z (n_105));
|
||||
CDN_bmux2 g53(.sel0 (ctrl_state$out[1]), .data0 (n_105), .data1
|
||||
(ctrl_state$out[0]), .z (ctrl_state$in_[0]));
|
||||
not g54 (n_108, resp_rdy);
|
||||
or g55 (n_109, n_108, ctrl_state$out[0]);
|
||||
and g56 (n_111, n_109, ctrl_state$out[1]);
|
||||
or g57 (n_110, n_103, n_2);
|
||||
not g58 (n_112, n_110);
|
||||
or g59 (ctrl_state$in_[1], n_111, n_112);
|
||||
CDN_bmux2 g220_dup_0(.sel0 (n_7), .data0 (resp_msg[0]), .data1
|
||||
(req_msg[16]), .z (n_476));
|
||||
CDN_bmux2 g220_dup_1(.sel0 (n_7), .data0 (dpath_b_reg$out[0]), .data1
|
||||
(req_msg[16]), .z (n_477));
|
||||
CDN_bmux2 g7_dup_0(.sel0 (n_7), .data0 (resp_msg[1]), .data1
|
||||
(req_msg[17]), .z (n_478));
|
||||
CDN_bmux2 g7_dup_1(.sel0 (n_7), .data0 (dpath_b_reg$out[1]), .data1
|
||||
(req_msg[17]), .z (n_479));
|
||||
CDN_bmux2 g10_dup_0(.sel0 (n_7), .data0 (resp_msg[2]), .data1
|
||||
(req_msg[18]), .z (n_480));
|
||||
CDN_bmux2 g10_dup_1(.sel0 (n_7), .data0 (dpath_b_reg$out[2]), .data1
|
||||
(req_msg[18]), .z (n_481));
|
||||
CDN_bmux2 g13_dup_0(.sel0 (n_7), .data0 (resp_msg[3]), .data1
|
||||
(req_msg[19]), .z (n_482));
|
||||
CDN_bmux2 g13_dup_1(.sel0 (n_7), .data0 (dpath_b_reg$out[3]), .data1
|
||||
(req_msg[19]), .z (n_483));
|
||||
CDN_bmux2 g16_dup_0(.sel0 (n_7), .data0 (resp_msg[4]), .data1
|
||||
(req_msg[20]), .z (n_484));
|
||||
CDN_bmux2 g16_dup_1(.sel0 (n_7), .data0 (dpath_b_reg$out[4]), .data1
|
||||
(req_msg[20]), .z (n_485));
|
||||
endmodule
|
||||
|
||||
`ifdef RC_CDN_GENERIC_GATE
|
||||
`else
|
||||
module CDN_flop(clk, d, sena, aclr, apre, srl, srd, q);
|
||||
input clk, d, sena, aclr, apre, srl, srd;
|
||||
output q;
|
||||
wire clk, d, sena, aclr, apre, srl, srd;
|
||||
wire q;
|
||||
reg qi;
|
||||
assign #1 q = qi;
|
||||
always
|
||||
@(posedge clk or posedge apre or posedge aclr)
|
||||
if (aclr)
|
||||
qi <= 0;
|
||||
else if (apre)
|
||||
qi <= 1;
|
||||
else if (srl)
|
||||
qi <= srd;
|
||||
else begin
|
||||
if (sena)
|
||||
qi <= d;
|
||||
end
|
||||
initial
|
||||
qi <= 1'b0;
|
||||
endmodule
|
||||
`endif
|
||||
`ifdef RC_CDN_GENERIC_GATE
|
||||
`else
|
||||
`ifdef ONE_HOT_MUX // captures one-hot property of select inputs
|
||||
module CDN_mux2(sel0, data0, sel1, data1, z);
|
||||
input sel0, data0, sel1, data1;
|
||||
output z;
|
||||
wire sel0, data0, sel1, data1;
|
||||
reg z;
|
||||
always
|
||||
@(sel0 or sel1 or data0 or data1)
|
||||
case ({sel0, sel1})
|
||||
2'b10: z = data0;
|
||||
2'b01: z = data1;
|
||||
default: z = 1'bX;
|
||||
endcase
|
||||
endmodule
|
||||
`else
|
||||
module CDN_mux2(sel0, data0, sel1, data1, z);
|
||||
input sel0, data0, sel1, data1;
|
||||
output z;
|
||||
wire sel0, data0, sel1, data1;
|
||||
wire z;
|
||||
wire w_0, w_1;
|
||||
and a_0 (w_0, sel0, data0);
|
||||
and a_1 (w_1, sel1, data1);
|
||||
or org (z, w_0, w_1);
|
||||
endmodule
|
||||
`endif // ONE_HOT_MUX
|
||||
`endif
|
||||
`ifdef RC_CDN_GENERIC_GATE
|
||||
`else
|
||||
`ifdef ONE_HOT_MUX
|
||||
module CDN_bmux2(sel0, data0, data1, z);
|
||||
input sel0, data0, data1;
|
||||
output z;
|
||||
wire sel0, data0, data1;
|
||||
reg z;
|
||||
always
|
||||
@(sel0 or data0 or data1)
|
||||
case ({sel0})
|
||||
1'b0: z = data0;
|
||||
1'b1: z = data1;
|
||||
endcase
|
||||
endmodule
|
||||
`else
|
||||
module CDN_bmux2(sel0, data0, data1, z);
|
||||
input sel0, data0, data1;
|
||||
output z;
|
||||
wire sel0, data0, data1;
|
||||
wire z;
|
||||
wire inv_sel0, w_0, w_1;
|
||||
not i_0 (inv_sel0, sel0);
|
||||
and a_0 (w_0, inv_sel0, data0);
|
||||
and a_1 (w_1, sel0, data1);
|
||||
or org (z, w_0, w_1);
|
||||
endmodule
|
||||
`endif // ONE_HOT_MUX
|
||||
`endif
|
||||
`ifdef RC_CDN_GENERIC_GATE
|
||||
`else
|
||||
`ifdef ONE_HOT_MUX
|
||||
module CDN_bmux4(sel0, data0, data1, sel1, data2, data3, z);
|
||||
input sel0, data0, data1, sel1, data2, data3;
|
||||
output z;
|
||||
wire sel0, data0, data1, sel1, data2, data3;
|
||||
reg z;
|
||||
always
|
||||
@(sel0 or sel1 or data0 or data1 or data2 or data3)
|
||||
case ({sel0, sel1})
|
||||
2'b00: z = data0;
|
||||
2'b10: z = data1;
|
||||
2'b01: z = data2;
|
||||
2'b11: z = data3;
|
||||
endcase
|
||||
endmodule
|
||||
`else
|
||||
module CDN_bmux4(sel0, data0, data1, sel1, data2, data3, z);
|
||||
input sel0, data0, data1, sel1, data2, data3;
|
||||
output z;
|
||||
wire sel0, data0, data1, sel1, data2, data3;
|
||||
wire z;
|
||||
wire inv_sel0, inv_sel1, w_0, w_1, w_2, w_3;
|
||||
not i_0 (inv_sel0, sel0);
|
||||
not i_1 (inv_sel1, sel1);
|
||||
and a_0 (w_0, inv_sel1, inv_sel0, data0);
|
||||
and a_1 (w_1, inv_sel1, sel0, data1);
|
||||
and a_2 (w_2, sel1, inv_sel0, data2);
|
||||
and a_3 (w_3, sel1, sel0, data3);
|
||||
or org (z, w_0, w_1, w_2, w_3);
|
||||
endmodule
|
||||
`endif // ONE_HOT_MUX
|
||||
`endif
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
Instance: /gcd
|
||||
Power Unit: W
|
||||
PDB Frames: /stim#0/frame#0
|
||||
-------------------------------------------------------------------------
|
||||
Category Leakage Internal Switching Total Row%
|
||||
-------------------------------------------------------------------------
|
||||
memory 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
register 1.86923e-06 1.98160e-03 0.00000e+00 1.98347e-03 53.24%
|
||||
latch 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
logic 2.34543e-06 1.73943e-03 0.00000e+00 1.74178e-03 46.76%
|
||||
bbox 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
clock 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
pad 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
pm 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
-------------------------------------------------------------------------
|
||||
Subtotal 4.21466e-06 3.72103e-03 0.00000e+00 3.72524e-03 100.00%
|
||||
Percentage 0.11% 99.89% 0.00% 100.00% 100.00%
|
||||
-------------------------------------------------------------------------
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
============================================================
|
||||
Generated by: Genus(TM) Synthesis Solution 19.12-s121_1
|
||||
Generated on: Aug 10 2020 11:16:47 am
|
||||
Module: gcd
|
||||
Technology library: gscl45nm
|
||||
Operating conditions: typical (balanced_tree)
|
||||
Wireload mode: enclosed
|
||||
Area mode: timing library
|
||||
============================================================
|
||||
|
||||
Pin Type Fanout Load Slew Delay Arrival
|
||||
(fF) (ps) (ps) (ps)
|
||||
-------------------------------------------------------------------------
|
||||
(clock clk) launch 0 R
|
||||
dpath_b_reg
|
||||
out_reg[1]/clk 400 0 R
|
||||
out_reg[1]/q (u) unmapped_d_flop 6 25.2 0 +191 191 F
|
||||
dpath_b_reg/out[1]
|
||||
dpath_sub_sub_752_15/B[1]
|
||||
g16/in_0 +0 191
|
||||
g16/z (u) unmapped_not 2 9.0 0 +42 233 R
|
||||
g23/in_1 +0 233
|
||||
g23/z (u) unmapped_nor2 1 4.2 0 +41 274 F
|
||||
g53/in_0 +0 274
|
||||
g53/z (u) unmapped_not 2 9.0 0 +42 316 R
|
||||
g54/in_1 +0 316
|
||||
g54/z (u) unmapped_nand2 1 4.2 0 +41 356 F
|
||||
g55/in_1 +0 356
|
||||
g55/z (u) unmapped_nand2 3 13.5 0 +58 414 R
|
||||
g87/in_1 +0 414
|
||||
g87/z (u) unmapped_nand2 1 4.2 0 +41 454 F
|
||||
g88/in_1 +0 454
|
||||
g88/z (u) unmapped_nand2 5 22.5 0 +65 519 R
|
||||
g128/in_0 +0 519
|
||||
g128/z (u) unmapped_nand2 1 4.2 0 +41 560 F
|
||||
g129/in_1 +0 560
|
||||
g129/z (u) unmapped_nand2 8 36.0 0 +76 636 R
|
||||
g162/in_1 +0 636
|
||||
g162/z (u) unmapped_nand2 1 4.2 0 +41 677 F
|
||||
g163/in_1 +0 677
|
||||
g163/z (u) unmapped_nand2 1 4.5 0 +41 718 R
|
||||
g203/in_0 +0 718
|
||||
g203/z (u) unmapped_xnor2 2 4.5 0 +76 794 R
|
||||
dpath_sub_sub_752_15/Z[15]
|
||||
g48/data0 +0 794
|
||||
g48/z (u) unmapped_bmux3 1 4.5 0 +76 870 R
|
||||
g49/data0 +0 870
|
||||
g49/z (u) unmapped_bmux3 1 4.5 0 +76 947 R
|
||||
dpath_a_reg/in_[15]
|
||||
g49_g1/data1 +0 947
|
||||
g49_g1/z (u) unmapped_mux4 1 4.5 0 +71 1018 R
|
||||
out_reg[15]/d <<< unmapped_d_flop +0 1018
|
||||
out_reg[15]/clk setup 400 +56 1074 R
|
||||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
||||
(clock clk) capture 100 R
|
||||
-------------------------------------------------------------------------
|
||||
Timing slack : -974ps (TIMING VIOLATION)
|
||||
Start-point : dpath_b_reg/out_reg[1]/clk
|
||||
End-point : dpath_a_reg/out_reg[15]/d
|
||||
|
||||
(u) : Net has unmapped pin(s).
|
||||
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
all:
|
||||
genus -legacy_ui -batch -files ../scripts/gcd_to_synth.tcl
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
source /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/scripts/gcd_to_floorplan.tcl
|
||||
source /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/scripts/gcd_to_pdn.tcl
|
||||
source /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/scripts/gcd_to_place.tcl
|
||||
source /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/scripts/gcd_to_cts.tcl
|
||||
source /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/scripts/gcd_to_route.tcl
|
||||
source /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/scripts/gcd_to_drc.tcl
|
||||
|
|
@ -0,0 +1 @@
|
|||
ccopt_design
|
||||
|
|
@ -0,0 +1 @@
|
|||
check_design -type all
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
set init_mmmc_file {/Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/objects/flow.view}
|
||||
set init_lef_file /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/lib/gscl45nm.lef
|
||||
set init_verilog /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/objects/gcd.vh
|
||||
set init_gnd_net "VSS"
|
||||
set init_pwr_net "VDD"
|
||||
init_design
|
||||
floorPlan
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
globalNetConnect VDD -type pgpin -pin VDD -inst * -verbose
|
||||
globalNetConnect VSS -type pgpin -pin VSS -inst * -verbose
|
||||
sroute -nets {VDD VSS}
|
||||
addRing -nets {VDD VSS} -width 0.6 -spacing 0.5 -layer [list top 7 bottom 7 left 6 right 6]
|
||||
addStripe -nets {VSS VDD} -layer 6 -direction vertical -width 0.4 -spacing 0.5 -set_to_set_distance 5 -start 0.5
|
||||
addStripe -nets {VSS VDD} -layer 7 -direction horizontal -width 0.4 -spacing 0.5 -set_to_set_distance 5 -start 0.5
|
||||
|
|
@ -0,0 +1 @@
|
|||
place_design -concurrent_macros -noPrePlaceOpt
|
||||
|
|
@ -0,0 +1 @@
|
|||
routeDesign -clockEco -globalDetail
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
set hdl_files {gcd.v}
|
||||
set DESIGN gcd
|
||||
set clkpin clk
|
||||
set delay 100
|
||||
set_attribute hdl_search_path /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/hdl
|
||||
set_attribute lib_search_path /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/lib
|
||||
set_attribute information_level 6
|
||||
set_attribute library gscl45nm.lib
|
||||
read_hdl ${hdl_files}
|
||||
elaborate $DESIGN
|
||||
set clock [define_clock -period ${delay} -name ${clkpin} [clock_ports]]
|
||||
external_delay -input 0 -clock clk [find / -port ports_in/*]
|
||||
external_delay -output 0 -clock clk [find / -port ports_out/*]
|
||||
dc::set_clock_transition .4 clk
|
||||
check_design -unresolved
|
||||
report timing -lint
|
||||
synthesize -to_mapped -effort -is_incremental
|
||||
report timing > /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/reports/timing_synth.rpt
|
||||
report gates > /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/reports/gates_synth.rpt
|
||||
report power > /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/reports/gates_synth.rpt
|
||||
write_hdl -mapped > /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/objects/gcd.vh
|
||||
write_sdc > /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/objects/gcd.sdc
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
read -sv /Users/daitoto/Desktop/code/DASYS/cocoon/demo/branch/../../data/gcd/hdl/gcd.v
|
||||
hierarchy -top gcd
|
||||
proc; opt; techmap; opt
|
||||
write_verilog /Users/daitoto/Desktop/code/DASYS/cocoon/demo/branch/../../data/gcd/gscl45nm/objects/gcd.v
|
||||
|
|
@ -0,0 +1 @@
|
|||
create_clock [get_ports clk] -name core_clock -period 10
|
||||
|
|
@ -1 +0,0 @@
|
|||
{"name":"sbt","version":"1.5.2","bspVersion":"2.0.0-M5","languages":["scala"],"argv":["/usr/lib/jvm/java-1.8.0-openjdk-1.8.0.312.b07-1.el7_9.x86_64/jre/bin/java","-Xms100m","-Xmx100m","-classpath","/home/wxm/.cache/sbt/boot/sbt-launch/1.5.5/sbt-launch-1.5.5.jar","xsbt.boot.Boot","-bsp","--sbt-launch-jar=/home/wxm/.cache/sbt/boot/sbt-launch/1.5.5/sbt-launch-1.5.5.jar"]}
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
# Default ignored files
|
||||
/shelf/
|
||||
/workspace.xml
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
<component name="ProjectCodeStyleConfiguration">
|
||||
<state>
|
||||
<option name="PREFERRED_PROJECT_CODE_STYLE" value="Default" />
|
||||
</state>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: com.github.nscala-time:nscala-time_2.12:2.22.0:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: com.github.scopt:scopt_2.12:3.7.1:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: com.google.protobuf:protobuf-java:3.9.0:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: com.lihaoyi:utest_2.12:0.6.7:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.7/utest_2.12-0.6.7.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.7/utest_2.12-0.6.7-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.7/utest_2.12-0.6.7-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: com.thoughtworks.paranamer:paranamer:2.8:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: edu.berkeley.cs:chisel3_2.12:3.4.1:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.4.1/chisel3_2.12-3.4.1.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.4.1/chisel3_2.12-3.4.1-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.4.1/chisel3_2.12-3.4.1-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: edu.berkeley.cs:chisel3-core_2.12:3.4.1:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.4.1/chisel3-core_2.12-3.4.1.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.4.1/chisel3-core_2.12-3.4.1-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.4.1/chisel3-core_2.12-3.4.1-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: edu.berkeley.cs:chisel3-macros_2.12:3.4.1:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.4.1/chisel3-macros_2.12-3.4.1.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.4.1/chisel3-macros_2.12-3.4.1-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.4.1/chisel3-macros_2.12-3.4.1-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: edu.berkeley.cs:chisel-iotesters_2.12:1.5.1:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.5.1/chisel-iotesters_2.12-1.5.1.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.5.1/chisel-iotesters_2.12-1.5.1-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.5.1/chisel-iotesters_2.12-1.5.1-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: edu.berkeley.cs:chiseltest_2.12:0.3.1:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.3.1/chiseltest_2.12-0.3.1.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.3.1/chiseltest_2.12-0.3.1-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.3.1/chiseltest_2.12-0.3.1-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: edu.berkeley.cs:firrtl_2.12:1.4.1:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.4.1/firrtl_2.12-1.4.1.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.4.1/firrtl_2.12-1.4.1-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.4.1/firrtl_2.12-1.4.1-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: edu.berkeley.cs:firrtl-interpreter_2.12:1.4.1:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.4.1/firrtl-interpreter_2.12-1.4.1.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.4.1/firrtl-interpreter_2.12-1.4.1-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.4.1/firrtl-interpreter_2.12-1.4.1-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: edu.berkeley.cs:treadle_2.12:1.3.1:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.3.1/treadle_2.12-1.3.1.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.3.1/treadle_2.12-1.3.1-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.3.1/treadle_2.12-1.3.1-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: joda-time:joda-time:2.10.1:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: junit:junit:4.13:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: net.jcazevedo:moultingyaml_2.12:0.4.2:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: org.antlr:antlr4-runtime:4.7.1:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: org.apache.commons:commons-lang3:3.9:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: org.apache.commons:commons-text:1.8:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: org.fusesource.jansi:jansi:1.11:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: org.hamcrest:hamcrest-core:1.3:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: org.joda:joda-convert:2.2.0:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: org.json4s:json4s-ast_2.12:3.6.9:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.9/json4s-ast_2.12-3.6.9.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.9/json4s-ast_2.12-3.6.9-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.9/json4s-ast_2.12-3.6.9-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: org.json4s:json4s-core_2.12:3.6.9:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.9/json4s-core_2.12-3.6.9.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.9/json4s-core_2.12-3.6.9-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.9/json4s-core_2.12-3.6.9-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: org.json4s:json4s-native_2.12:3.6.9:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.9/json4s-native_2.12-3.6.9.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.9/json4s-native_2.12-3.6.9-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.9/json4s-native_2.12-3.6.9-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: org.json4s:json4s-scalap_2.12:3.6.9:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.9/json4s-scalap_2.12-3.6.9.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.9/json4s-scalap_2.12-3.6.9-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.9/json4s-scalap_2.12-3.6.9-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: org.portable-scala:portable-scala-reflect_2.12:0.1.0:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: org.scala-lang.modules:scala-jline:2.12.1:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: org.scala-lang.modules:scala-xml_2.12:1.2.0:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: org.scala-lang:scala-library:2.12.12:jar" type="Scala">
|
||||
<properties>
|
||||
<compiler-classpath>
|
||||
<root url="file://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/jline/jline/2.14.6/jline-2.14.6.jar" />
|
||||
<root url="file://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.12/jansi-1.12.jar" />
|
||||
<root url="file://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.0.6/scala-xml_2.12-1.0.6.jar" />
|
||||
<root url="file://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-compiler/2.12.12/scala-compiler-2.12.12.jar" />
|
||||
<root url="file://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.12/scala-library-2.12.12.jar" />
|
||||
<root url="file://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.12.12/scala-reflect-2.12.12.jar" />
|
||||
</compiler-classpath>
|
||||
</properties>
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.12/scala-library-2.12.12.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.12/scala-library-2.12.12-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.12/scala-library-2.12.12-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: org.scala-lang:scala-reflect:2.12.12:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.12.12/scala-reflect-2.12.12.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.12.12/scala-reflect-2.12.12-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.12.12/scala-reflect-2.12.12-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: org.scala-sbt:test-interface:1.0:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: org.scalacheck:scalacheck_2.12:1.14.3:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: org.scalactic:scalactic_2.12:3.0.8:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: org.scalatest:scalatest_2.12:3.0.8:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<component name="libraryTable">
|
||||
<library name="sbt: org.yaml:snakeyaml:1.26:jar">
|
||||
<CLASSES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26-javadoc.jar!/" />
|
||||
</JAVADOC>
|
||||
<SOURCES>
|
||||
<root url="jar://$PROJECT_DIR$/../.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26-sources.jar!/" />
|
||||
</SOURCES>
|
||||
</library>
|
||||
</component>
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<project version="4">
|
||||
<component name="ProjectRootManager" version="2" languageLevel="JDK_11" default="true" project-jdk-name="11" project-jdk-type="JavaSDK" />
|
||||
</project>
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<project version="4">
|
||||
<component name="ProjectModuleManager">
|
||||
<modules>
|
||||
<module fileurl="file://$PROJECT_DIR$/.idea/modules/alu-chisel.iml" filepath="$PROJECT_DIR$/.idea/modules/alu-chisel.iml" />
|
||||
<module fileurl="file://$PROJECT_DIR$/.idea/modules/alu-chisel-build.iml" filepath="$PROJECT_DIR$/.idea/modules/alu-chisel-build.iml" />
|
||||
</modules>
|
||||
</component>
|
||||
</project>
|
||||
|
|
@ -1,116 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<module external.linked.project.id="alu-chisel-build" external.linked.project.path="$MODULE_DIR$/../../project" external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" sbt.imports="_root_.sbt.Keys._, _root_.sbt.ScriptedPlugin.autoImport._, _root_.sbt.plugins.JUnitXmlReportPlugin.autoImport._, _root_.sbt.plugins.MiniDependencyTreePlugin.autoImport._, _root_.sbt._, _root_.sbt.nio.Keys._, _root_.sbt.plugins.IvyPlugin, _root_.sbt.plugins.JvmPlugin, _root_.sbt.plugins.CorePlugin, _root_.sbt.ScriptedPlugin, _root_.sbt.plugins.SbtPlugin, _root_.sbt.plugins.SemanticdbPlugin, _root_.sbt.plugins.JUnitXmlReportPlugin, _root_.sbt.plugins.Giter8TemplatePlugin, _root_.sbt.plugins.MiniDependencyTreePlugin, _root_.scala.xml.{TopScope=&gt;SUB:DOLLARscope}" sbt.resolvers="https://oss.sonatype.org/content/repositories/releases|maven|sonatype-releases, https://oss.sonatype.org/content/repositories/snapshots|maven|sonatype-snapshots, /home/wxm/.ivy2/cache|ivy|Local cache, file:/home/wxm/.sbt/preloaded|maven|local-preloaded, https://repo1.maven.org/maven2/|maven|public" type="SBT_MODULE" version="4">
|
||||
<component name="NewModuleRootManager">
|
||||
<output url="file://$MODULE_DIR$/../../project/target/idea-classes" />
|
||||
<output-test url="file://$MODULE_DIR$/../../project/target/idea-test-classes" />
|
||||
<exclude-output />
|
||||
<content url="file://$MODULE_DIR$/../../project">
|
||||
<sourceFolder url="file://$MODULE_DIR$/../../project" isTestSource="false" />
|
||||
<excludeFolder url="file://$MODULE_DIR$/../../project/project/target" />
|
||||
<excludeFolder url="file://$MODULE_DIR$/../../project/target" />
|
||||
</content>
|
||||
<orderEntry type="inheritedJdk" />
|
||||
<orderEntry type="sourceFolder" forTests="false" />
|
||||
<orderEntry type="module-library">
|
||||
<library name="sbt: sbt-and-plugins">
|
||||
<CLASSES>
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/lib/scala-compiler.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/lib/scala-library.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/lib/scala-reflect.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/lib/scala-xml_2.12-1.0.6.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/actions_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/caffeine-2.8.5.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/checker-qual-3.4.1.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/collections_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/command_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/compiler-bridge_2.12-1.5.3.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/compiler-interface-1.5.3.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/completion_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/config-1.3.3.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/core-macros_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/disruptor-3.4.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/error_prone_annotations-2.4.0.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/file-tree-views-2.1.6.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/gigahorse-core_2.12-0.5.0.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/gigahorse-okhttp_2.12-0.5.0.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/io_2.12-1.5.0.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/ipcsocket-1.3.0.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/ivy-2.3.0-sbt-fbc4f586aeeb1591710b14eb4f41b94880dcd745.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/jansi-2.1.0.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/jline-2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/jline-builtins-3.19.0.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/jline-reader-3.19.0.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/jline-style-3.19.0.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/jline-terminal-3.19.0.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/jline-terminal-jansi-3.19.0.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/jline-terminal-jna-3.19.0.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/jna-5.5.0.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/jna-platform-5.5.0.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/jsch-0.1.54.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/launcher-interface-1.3.1.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/librarymanagement-core_2.12-1.5.0.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/librarymanagement-ivy_2.12-1.5.0.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/lm-coursier-shaded_2.12-2.0.8.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/log4j-api-2.11.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/log4j-core-2.11.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/log4j-slf4j-impl-2.11.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/logic_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/main-settings_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/main_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/okhttp-3.14.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/okhttp-urlconnection-3.7.0.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/okio-1.17.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/protocol_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/reactive-streams-1.0.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/run_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/sbinary_2.12-0.5.1.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/sbt-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/scala-collection-compat_2.12-2.4.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/scala-compiler-2.12.13.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/scala-library-2.12.13.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/scala-parser-combinators_2.12-1.1.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/scala-reflect-2.12.13.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/scala-xml_2.12-1.3.0.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/scripted-plugin_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/shaded-jawn-parser_2.12-0.9.1.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/shaded-scalajson_2.12-1.0.0-M4.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/sjson-new-core_2.12-0.9.1.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/sjson-new-murmurhash_2.12-0.9.1.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/sjson-new-scalajson_2.12-0.9.1.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/slf4j-api-1.7.26.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/ssl-config-core_2.12-0.4.0.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/task-system_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/tasks_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/template-resolver-0.1.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/test-agent-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/test-interface-1.0.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/testing_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/util-cache_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/util-control_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/util-interface-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/util-logging_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/util-position_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/util-relation_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/util-tracking_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/zero-allocation-hashing-0.10.1.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/zinc-apiinfo_2.12-1.5.3.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/zinc-classfile_2.12-1.5.3.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/zinc-classpath_2.12-1.5.3.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/zinc-compile-core_2.12-1.5.3.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/zinc-compile_2.12-1.5.3.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/zinc-core_2.12-1.5.3.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/zinc-lm-integration_2.12-1.5.2.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/zinc-persist-core-assembly-1.5.3.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/zinc-persist_2.12-1.5.3.jar!/" />
|
||||
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.13/org.scala-sbt/sbt/1.5.2/zinc_2.12-1.5.3.jar!/" />
|
||||
</CLASSES>
|
||||
<JAVADOC />
|
||||
<SOURCES />
|
||||
</library>
|
||||
</orderEntry>
|
||||
</component>
|
||||
<component name="SbtModule">
|
||||
<option name="buildForURI" value="file:$MODULE_DIR$/../../" />
|
||||
<option name="imports" value="_root_.sbt.Keys._, _root_.sbt.ScriptedPlugin.autoImport._, _root_.sbt.plugins.JUnitXmlReportPlugin.autoImport._, _root_.sbt.plugins.MiniDependencyTreePlugin.autoImport._, _root_.sbt._, _root_.sbt.nio.Keys._, _root_.sbt.plugins.IvyPlugin, _root_.sbt.plugins.JvmPlugin, _root_.sbt.plugins.CorePlugin, _root_.sbt.ScriptedPlugin, _root_.sbt.plugins.SbtPlugin, _root_.sbt.plugins.SemanticdbPlugin, _root_.sbt.plugins.JUnitXmlReportPlugin, _root_.sbt.plugins.Giter8TemplatePlugin, _root_.sbt.plugins.MiniDependencyTreePlugin, _root_.scala.xml.{TopScope=>SUB:DOLLARscope}" />
|
||||
</component>
|
||||
</module>
|
||||
|
|
@ -1,50 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<module external.linked.project.id="alu-chisel [file:/home/wxm/alu-chisel/]" external.linked.project.path="$MODULE_DIR$/../.." external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" type="JAVA_MODULE" version="4">
|
||||
<component name="NewModuleRootManager" LANGUAGE_LEVEL="JDK_11">
|
||||
<output url="file://$MODULE_DIR$/../../target/scala-2.12/classes" />
|
||||
<output-test url="file://$MODULE_DIR$/../../target/scala-2.12/test-classes" />
|
||||
<exclude-output />
|
||||
<content url="file://$MODULE_DIR$/../..">
|
||||
<sourceFolder url="file://$MODULE_DIR$/../../src/main/scala" isTestSource="false" />
|
||||
<excludeFolder url="file://$MODULE_DIR$/../../target" />
|
||||
</content>
|
||||
<orderEntry type="inheritedJdk" />
|
||||
<orderEntry type="sourceFolder" forTests="false" />
|
||||
<orderEntry type="library" name="sbt: com.github.nscala-time:nscala-time_2.12:2.22.0:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: com.github.scopt:scopt_2.12:3.7.1:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: com.google.protobuf:protobuf-java:3.9.0:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: com.lihaoyi:utest_2.12:0.6.7:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: com.thoughtworks.paranamer:paranamer:2.8:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: edu.berkeley.cs:chisel-iotesters_2.12:1.5.1:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: edu.berkeley.cs:chisel3-core_2.12:3.4.1:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: edu.berkeley.cs:chisel3-macros_2.12:3.4.1:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: edu.berkeley.cs:chisel3_2.12:3.4.1:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: edu.berkeley.cs:chiseltest_2.12:0.3.1:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: edu.berkeley.cs:firrtl-interpreter_2.12:1.4.1:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: edu.berkeley.cs:firrtl_2.12:1.4.1:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: edu.berkeley.cs:treadle_2.12:1.3.1:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: joda-time:joda-time:2.10.1:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: junit:junit:4.13:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: net.jcazevedo:moultingyaml_2.12:0.4.2:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: org.antlr:antlr4-runtime:4.7.1:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: org.apache.commons:commons-lang3:3.9:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: org.apache.commons:commons-text:1.8:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: org.fusesource.jansi:jansi:1.11:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: org.hamcrest:hamcrest-core:1.3:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: org.joda:joda-convert:2.2.0:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: org.json4s:json4s-ast_2.12:3.6.9:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: org.json4s:json4s-core_2.12:3.6.9:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: org.json4s:json4s-native_2.12:3.6.9:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: org.json4s:json4s-scalap_2.12:3.6.9:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: org.portable-scala:portable-scala-reflect_2.12:0.1.0:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: org.scala-lang.modules:scala-jline:2.12.1:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: org.scala-lang.modules:scala-xml_2.12:1.2.0:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: org.scala-lang:scala-library:2.12.12:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: org.scala-lang:scala-reflect:2.12.12:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: org.scala-sbt:test-interface:1.0:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: org.scalacheck:scalacheck_2.12:1.14.3:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: org.scalactic:scalactic_2.12:3.0.8:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: org.scalatest:scalatest_2.12:3.0.8:jar" level="project" />
|
||||
<orderEntry type="library" name="sbt: org.yaml:snakeyaml:1.26:jar" level="project" />
|
||||
</component>
|
||||
</module>
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<project version="4">
|
||||
<component name="RunConfigurationProducerService">
|
||||
<option name="ignoredProducers">
|
||||
<set>
|
||||
<option value="com.android.tools.idea.compose.preview.runconfiguration.ComposePreviewRunConfigurationProducer" />
|
||||
</set>
|
||||
</option>
|
||||
</component>
|
||||
</project>
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<project version="4">
|
||||
<component name="ScalaSbtSettings">
|
||||
<option name="customVMPath" />
|
||||
<option name="linkedExternalProjectsSettings">
|
||||
<SbtProjectSettings>
|
||||
<option name="externalProjectPath" value="$PROJECT_DIR$" />
|
||||
<option name="modules">
|
||||
<set>
|
||||
<option value="$PROJECT_DIR$" />
|
||||
<option value="$PROJECT_DIR$/project" />
|
||||
</set>
|
||||
</option>
|
||||
<option name="sbtVersion" value="1.5.2" />
|
||||
</SbtProjectSettings>
|
||||
</option>
|
||||
</component>
|
||||
</project>
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<project version="4">
|
||||
<component name="ScalaCompilerConfiguration">
|
||||
<profile name="sbt 1" modules="chisel-examples_6588" />
|
||||
<profile name="sbt 2" modules="alu-chisel,chisel-examples">
|
||||
<option name="deprecationWarnings" value="true" />
|
||||
<parameters>
|
||||
<parameter value="-Xsource:2.11" />
|
||||
</parameters>
|
||||
</profile>
|
||||
</component>
|
||||
</project>
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<project version="4">
|
||||
<component name="VcsDirectoryMappings">
|
||||
<mapping directory="" vcs="Git" />
|
||||
</component>
|
||||
</project>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
#
|
||||
# Building Chisel examples without too much sbt/scala/... stuff
|
||||
#
|
||||
# sbt looks for default into a folder ./project and . for build.sdt and Build.scala
|
||||
# sbt creates per default a ./target folder
|
||||
|
||||
SBT = sbt
|
||||
|
||||
|
||||
# Generate Verilog code
|
||||
|
||||
alu:
|
||||
$(SBT) "runMain AluTop"
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
scalaVersion := "2.12.12"
|
||||
|
||||
scalacOptions := Seq("-deprecation", "-Xsource:2.11")
|
||||
|
||||
resolvers ++= Seq(
|
||||
Resolver.sonatypeRepo("snapshots"),
|
||||
Resolver.sonatypeRepo("releases")
|
||||
)
|
||||
|
||||
// Chisel 3.4
|
||||
libraryDependencies += "edu.berkeley.cs" %% "chisel-iotesters" % "1.5.1"
|
||||
libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.3.1"
|
||||
|
|
@ -1 +0,0 @@
|
|||
sbt.version=1.5.2
|
||||
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Reference in New Issue