add partition subflow

code.bak/logiccommander.py

@@ -0,0 +1,46 @@
+class MySubFlow(object):
+    def __init__(self):
+        self.ops = []
+
+    def flow(self):
+        op_syn = opsrc.op.logiccommander
+        self.ops.append(op_syn)
+        
+
+class MyFlow(object):
+    
+    def __init__(self):
+        self.ops = []
+        self.des_list = []
+    
+
+    def flow(self):
+        des_list = op.min_cut_partition(design)
+
+        for x in des_list:
+            sub_flow = MySubFlow()
+            sub_ops = sub_flow.ops
+            ops.append(sub_ops)
+
+        #merge?
+
+
+        op_floorplan = cds.op.innovus.floorplan
+        ops.append(op_floorplan)
+
+        op_place = opsrc.op.dreamplace
+        ops.append(op_place)
+
+        op_cts = cds.op.cts
+        ops.append(op_place)
+
+        op_route = cds.op.route
+        ops.append(op_place)
+        
+        op_drc = cds.op.innovus.op_drc
+        ops.append(op_drc)
+        
+
+
+
+    

code.bak/sys_place.py

@@ -0,0 +1,41 @@
+class MySubFlow(object):
+    def __init__(self):
+        self.ops = []
+
+    def flow(self):
+        op_cts = cds.op.cts
+        self.ops.append(op_cts)
+        op_route = cds.op.route
+        self.ops.append(op_route)
+
+class MyFlow(object):
+    
+    def __init__(self):
+        self.ops = []
+        self.des_list = []
+    
+
+    def flow(self):
+        des_list = op.min_cut_partition(design)
+
+        op_syn = cds.op.genus
+        ops.append(op_syn)
+
+        op_floorplan = cds.op.innovus.floorplan
+        ops.append(op_floorplan)
+
+        op_place = opsrc.op.dreamplace
+        ops.append(op_place)
+
+        for x in des_list:
+            sub_flow = MySubFlow()
+            sub_ops = sub_flow.ops
+            ops.append(sub_ops)
+        
+        op_drc = cds.op.innovus.op_drc
+        ops.append(op_drc)
+        
+
+
+
+    

code.bak/test.py

@@ -0,0 +1 @@
+import numpy

data/gcd/gscl45nm/run/Makefile

@@ -1,2 +1,2 @@
 all:
-	yosys ../scripts/gcd_to_synth.ys
+	genus -legacy_ui -batch -files ../scripts/gcd_to_synth.tcl

data/gcd/gscl45nm/scripts/flow.tcl

@@ -0,0 +1,6 @@
+source /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/scripts/gcd_to_floorplan.tcl
+source /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/scripts/gcd_to_pdn.tcl
+source /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/scripts/gcd_to_place.tcl
+source /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/scripts/gcd_to_cts.tcl
+source /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/scripts/gcd_to_route.tcl
+source /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/scripts/gcd_to_drc.tcl

data/gcd/gscl45nm/scripts/gcd_to_cts.tcl

@@ -0,0 +1 @@
+ccopt_design

data/gcd/gscl45nm/scripts/gcd_to_drc.tcl

@@ -0,0 +1 @@
+check_design -type all

data/gcd/gscl45nm/scripts/gcd_to_floorplan.tcl

@@ -0,0 +1,7 @@
+set init_mmmc_file {/Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/objects/flow.view}
+set init_lef_file /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/lib/gscl45nm.lef
+set init_verilog /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/objects/gcd.vh
+set init_gnd_net "VSS"
+set init_pwr_net "VDD"
+init_design
+floorPlan

data/gcd/gscl45nm/scripts/gcd_to_pdn.tcl

@@ -0,0 +1,6 @@
+globalNetConnect VDD -type pgpin -pin VDD -inst * -verbose
+globalNetConnect VSS -type pgpin -pin VSS -inst * -verbose
+sroute -nets {VDD VSS}
+addRing -nets {VDD VSS} -width 0.6 -spacing 0.5 -layer [list top 7 bottom 7 left 6 right 6]
+addStripe -nets {VSS VDD} -layer 6 -direction vertical -width 0.4 -spacing 0.5 -set_to_set_distance 5 -start 0.5
+addStripe -nets {VSS VDD} -layer 7 -direction horizontal -width 0.4 -spacing 0.5 -set_to_set_distance 5 -start 0.5

data/gcd/gscl45nm/scripts/gcd_to_place.tcl

@@ -0,0 +1 @@
+place_design -concurrent_macros -noPrePlaceOpt

data/gcd/gscl45nm/scripts/gcd_to_route.tcl

@@ -0,0 +1 @@
+routeDesign -clockEco -globalDetail

data/gcd/gscl45nm/scripts/gcd_to_synth.tcl

@@ -2,8 +2,8 @@ set hdl_files {gcd.v}
 set DESIGN gcd
 set clkpin clk
 set delay 100
-set_attribute hdl_search_path /home/jxzhang/projects/cocoon/design/gcd/hdl
-set_attribute lib_search_path /home/jxzhang/projects/cocoon/design/lib
+set_attribute hdl_search_path /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/hdl
+set_attribute lib_search_path /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/lib
 set_attribute information_level 6 
 set_attribute library gscl45nm.lib
 read_hdl ${hdl_files} 
@@ -14,9 +14,9 @@ external_delay -output  0 -clock clk [find / -port ports_out/*]
 dc::set_clock_transition .4 clk
 check_design -unresolved
 report timing -lint
-synthesize -effort -is_incremental
-report timing > /home/jxzhang/projects/cocoon/design/gcd/gscl45nm/reports/timing_synth.rpt
-report gates  > /home/jxzhang/projects/cocoon/design/gcd/gscl45nm/reports/gates_synth.rpt
-report power  > /home/jxzhang/projects/cocoon/design/gcd/gscl45nm/reports/gates_synth.rpt
-write_hdl -mapped >  /home/jxzhang/projects/cocoon/design/gcd/gscl45nm/objects/gcd.vh
-write_sdc >  /home/jxzhang/projects/cocoon/design/gcd/gscl45nm/objects/gcd_synth.sdc
+synthesize -to_mapped -effort -is_incremental
+report timing > /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/reports/timing_synth.rpt
+report gates  > /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/reports/gates_synth.rpt
+report power  > /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/reports/gates_synth.rpt
+write_hdl -mapped >  /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/objects/gcd.vh
+write_sdc >  /Users/daitoto/Desktop/code/DASYS/cocoon/demo/tuner/../../data/gcd/gscl45nm/objects/gcd.sdc

data/gcd/gscl45nm/scripts/gcd_to_synth.ys

@@ -1,4 +1,4 @@
-read -sv /Users/daitoto/Desktop/code/DASYS/cocoon/data/gcd/hdl/gcd.v
+read -sv /Users/daitoto/Desktop/code/DASYS/cocoon/demo/branch/../../data/gcd/hdl/gcd.v
 hierarchy -top gcd
 proc; opt; techmap; opt
-write_verilog /Users/daitoto/Desktop/code/DASYS/cocoon/data/gcd/gscl45nm/objects/gcd.v
+write_verilog /Users/daitoto/Desktop/code/DASYS/cocoon/demo/branch/../../data/gcd/gscl45nm/objects/gcd.v

demo/branch/flow.py

@@ -4,6 +4,7 @@ from designcfg import Design
 import engine
 import subprocess, os
 import util
+util.home_path = util.home_path + "/../.."
 
 #define a customized flow
 class MyFlow(object):

demo/tuner/main.py

@@ -5,6 +5,7 @@ import engine
 import util
 from myflow import MyFlow
 from designcfg import Design
+util.home_path = util.home_path + "/../.."
 
 space = {
     # syn
@@ -17,11 +18,10 @@ space = {
     "place_nop": hp.choice("place_x3", [True, False]),
     # route
     "route_gd": hp.choice("route_x1", [True, False]),
-    "route_detail": hp.choice("route_x2", [True, False]),
     "route_clock": hp.choice("route_x3", [True, False])
 }
 
-design = Design("cgra")
+design = Design("gcd")
 
 def optFunc(args):
 
@@ -36,7 +36,6 @@ def optFunc(args):
     flow.params_place.append(("noPrePlaceOpt", args["place_nop"]))
 
     flow.params_route.append(("globalDetail", args["route_gd"]))
-    flow.params_route.append(("detail", args["route_detail"]))
     flow.params_route.append(("clockEco", args["route_clock"]))
 
     ckpt = engine.run(design, flow)

ecc_flow.py

@@ -0,0 +1,44 @@
+from designcfg import Design
+import engine
+import subprocess, os
+
+#define a customized flow
+class EccFlow(object):
+
+    def __init__(self):
+        self.ops = []
+        self.params_syn = []
+        self.params_fp = []
+        self.params_pdn = []
+        self.params_place = []
+        self.params_cts = []
+        self.params_route = []
+        self.params_drc = []
+
+    def flow(self):
+
+        op_synth = Vivado.op.synth
+        self.ops.append((op_synth, "to_synth")) 
+        
+        op_floorplan = Vivado.op.floorplan
+        self.params_fp = [("mul_xy", "SLR0"), ("mul_yz", "SLR1"), ("mul_xx", "SLR2")] # SLR partition constrains
+        self.ops.append((op_floorplan, "to_fp"))
+
+        op_place_0 = DIY.op.placeRegSLR # user define placer for regs. of inter-SLRs
+        self.ops.append((op_place_0, "to_placeRegSLR"))
+        op_place_1 = Vivado.op.place
+        self.ops.append((op_place_1, "to_place"))
+
+        op_route = Vivado.op.route
+        self.ops.append((op_route, "to_route"))
+
+
+if __name__ == "__main__":
+
+    design = Design("gcd")
+
+    my_flow = EccFlow()
+    my_flow.flow()
+
+    res = engine.run(design, my_flow)
+

engine.py

@@ -48,11 +48,11 @@ def run(design, flow):
             overall_tcl.write('source %s/%s_to_pdn.tcl\n'%(tcl_path, design_name))
 
         if x[0] == "InnovusPlace":
-            tmp_op_pdn = eval("place1." + "InnovusPlace" + "(design)")
-            for param in flow.params_syn:
+            tmp_op_place = eval("place1." + "InnovusPlace" + "(design)")
+            for param in flow.params_place:
                 if param[1] == True:
-                    tmp_op_syn.setParams(param[0])
-            tmp_op_pdn.config(design, design_name + "_" + x[1])
+                    tmp_op_place.setParams(param[0])
+            tmp_op_place.config(design, design_name + "_" + x[1])
             overall_tcl.write('source %s/%s_to_place.tcl\n'%(tcl_path, design_name))
 
         if x[0] == "InnovusCTS":
@@ -62,9 +62,8 @@ def run(design, flow):
 
         if x[0] == "InnovusRoute":
             tmp_op_route = eval("route1." + "InnovusRoute" + "(design)")
-            for param in flow.params_syn:
-                if param[1] == True:
-                    tmp_op_syn.setParams(param[0])
+            for param in flow.params_route:
+                tmp_op_route.setParams(param[0], param[1])
             tmp_op_route.config(design, design_name + "_" + x[1])
             overall_tcl.write('source %s/%s_to_route.tcl\n'%(tcl_path, design_name))
 
@@ -86,5 +85,5 @@ def run(design, flow):
     #subprocess.Popen(cmd)
     subprocess.Popen(cmd, shell=True).wait()
 
-    return 0
+    return design
 

graph/branch.py

@@ -0,0 +1,44 @@
+import cocoon as cc
+from cc.design import Design
+
+class BranchFlow(object):
+    def __init__(self, cfg):
+        self.cfg = cfg
+        self.syn_op1 = cc.ops.cds.synth
+        self.syn_op2 = cc.ops.yosys.synth
+        self.syn_cmp = "Timing" #compare timing
+        self.syn_para = dict()
+        self.flp_op = cc.ops.cds.flp
+        self.flp_para = dict()
+        # self.pdn_ckpt = cc.ops.cds.pdn
+        self.place_op = cc.ops.cds.place
+        self.place_para = dict()
+        self.cts_op = cc.ops.cds.cts
+        self.cts_para = dict()
+        self.route_op = cc.ops.cds.route
+        self.route_para = dict()
+        self.drc_op = cc.ops.cds.drc
+        pass
+
+    def build_flow(self, inp):
+        syn_ckpt1 = self.syn_op1(inp, self.syn_para)
+        syn_ckpt2 = self.syn_op2(inp, self.syn_para)
+        # compare here
+        syn_ckpt = cc.ops.cmp(syn_ckpt1, syn_ckpt2, self.syn_cmp)
+        # syn_ckpt.save(path)
+        flp_ckpt = self.flp_op(syn_ckpt, self.flp_para)
+        place_ckpt = self.place_op(flp_ckpt, self.place_para)
+        cts_ckpt = self.cts_op(place_ckpt, self.cts_para)
+        route_ckpt = self.route_op(cts_ckpt, self.route_para)
+        drc_ckpt = self.drc_op(route_ckpt)
+        return drc_ckpt
+
+def main():
+    cfg = {"path": "..."}
+    design = Design(cfg)
+    mf = MyFlow(cfg)
+    ckpt = mf.build_flow(design)
+    cc.engine.run(ckpt)
+
+if __name__ == "__main__":
+    main()

graph/flow.py

@@ -0,0 +1,39 @@
+import cocoon as cc
+from cc.design import Design
+
+class MyFlow(object):
+    def __init__(self, cfg):
+        self.cfg = cfg
+        self.syn_op = cc.ops.cds.synth
+        self.syn_para = dict()
+        self.flp_op = cc.ops.cds.flp
+        self.flp_para = dict()
+        # self.pdn_ckpt = cc.ops.cds.pdn
+        self.place_op = cc.ops.cds.place
+        self.place_para = dict()
+        self.cts_op = cc.ops.cds.cts
+        self.cts_para = dict()
+        self.route_op = cc.ops.cds.route
+        self.route_para = dict()
+        self.drc_op = cc.ops.cds.drc
+        pass
+
+    def build_flow(self, inp):
+        syn_ckpt = self.syn_op(inp, self.syn_para)
+        # syn_ckpt.save(path)
+        flp_ckpt = self.flp_op(syn_ckpt, self.flp_para)
+        place_ckpt = self.place_op(flp_ckpt, self.place_para)
+        cts_ckpt = self.cts_op(place_ckpt, self.cts_para)
+        route_ckpt = self.route_op(cts_ckpt, self.route_para)
+        drc_ckpt = self.drc_op(route_ckpt)
+        return drc_ckpt
+
+def main():
+    cfg = {"path": "..."}
+    design = Design(cfg)
+    mf = MyFlow(cfg)
+    ckpt = mf.build_flow(design)
+    cc.engine.run(ckpt)
+
+if __name__ == "__main__":
+    main()

graph/partition.py

@@ -0,0 +1,54 @@
+import cocoon as cc
+from cc.design import Design
+
+class MyFlow(object):
+    def __init__(self, cfg):
+        self.cfg = cfg
+        self.syn_op = cc.ops.cds.synth
+        self.syn_para = dict()
+        self.flp_op = cc.ops.cds.flp
+        self.flp_para = dict()
+        self.part_op = cc.ops.part
+        # self.pdn_ckpt = cc.ops.cds.pdn
+        self.place_op1 = cc.ops.cds.place
+        self.place_para1 = dict()
+        self.place_op2 = cc.ops.dream_place.place
+        self.place_para2 = dict()
+        self.place_op3 = cc.ops.ntu.place
+        self.place_para3 = dict()
+        self.merge_op = cc.ops.merge
+        self.cts_op = cc.ops.cds.cts
+        self.cts_para = dict()
+        self.route_op = cc.ops.cds.route
+        self.route_para = dict()
+        self.drc_op = cc.ops.cds.drc
+        pass
+
+    def build_flow(self, inp):
+        syn_ckpt = self.syn_op(inp, self.syn_para)
+        # syn_ckpt.save(path)
+        flp_ckpt = self.flp_op(syn_ckpt, self.flp_para)
+        
+        # partition
+        part1, part2, part3 = self.part_op(flp_ckpt, 3)
+        # subflow
+        place_ckpt1 = self.place_op1(part1, self.place_para1)
+        place_ckpt2 = self.place_op1(part2, self.place_para2)
+        place_ckpt3 = self.place_op1(part3, self.place_para3)
+        # merge
+        place_ckpt = self.merge_op([place_ckpt1, place_ckpt2, place_ckpt3])
+
+        cts_ckpt = self.cts_op(place_ckpt, self.cts_para)
+        route_ckpt = self.route_op(cts_ckpt, self.route_para)
+        drc_ckpt = self.drc_op(route_ckpt)
+        return drc_ckpt
+
+def main():
+    cfg = {"path": "..."}
+    design = Design(cfg)
+    mf = MyFlow(cfg)
+    ckpt = mf.build_flow(design)
+    cc.engine.run(ckpt)
+
+if __name__ == "__main__":
+    main()

graph/ui.md

@@ -0,0 +1,13 @@
+cocoon
+|---    ops    // operations, including compare operation
+|---    engine // run computational graph
+|---    ckpt   // checkpoint
+        |----   design files
+        |----   operation commands
+        |----   report files
+        |----   log files
+        |----   legality check information
+|---    design // input design, a special ckpt
+        |----   design files
+|---    result // for tuning
+

util.py

@@ -38,6 +38,7 @@ def getLefPath(design, baseflow):
     return lef_path
 
 def getRptPath(design, baseflow):
+    rpt_path = home_path + "/data/" + design.top_name + "/" + design.lib_name + "/reports"
     if baseflow == "Cadence":
         rpt_path = home_path + "/data/" + design.top_name + "/" + design.lib_name + "/reports"
     elif baseflow == "Yosys":
@@ -69,6 +70,7 @@ def getResult(design, optFunc, baseFlow):
     if optFunc == "Timing":
         rpt = getRptPath(design, baseFlow)
         res = rpt + "/timing.rpt"
+    res = 1000
     return res
 
 def evaluate(ckpt_list, optFunc, baseFlow):