fix yosys bugs

This commit is contained in:
zjxzjxzjx 2020-08-30 21:24:55 +08:00
parent 1e12c99beb
commit d9dbd7a4b6
6 changed files with 43 additions and 33 deletions

View File

@ -3,7 +3,7 @@ class Design(object):
def __init__(self, top_name):
self.top_name = top_name
self.lib_name = "gscl45nm"
self.rtl_file = "{gcd.v}"
self.rtl_file = "gcd.v"
#self.hdl_path = "./design/gcd/hdl"
#self.lib_path = "./design/lib"
self.mmmc_file = "flow.view"

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@ -8,7 +8,7 @@ import ops.cds.place as place1
import ops.cds.cts as cts1
import ops.cds.route as route1
import ops.cds.drc as drc1
import ops.openroad.syn as syn2
import ops.opensource.syn.yosys as syn2
def run(design, flow):
design_name = design.top_name
@ -24,7 +24,13 @@ def run(design, flow):
tmp_op_syn.config(design, design_name + "_" + x[1])
make_file.write("all:\n")
make_file.write("\tgenus -legacy_ui -batch -files " + script_path + design_name + "_" + x[1] + ".tcl\n")
#if x[0] == "OpenROADSynth":
if x[0] == "YosysSynth":
script_path = "../scripts/"
tmp_op_syn = eval("syn2." + "YosysSynth" + "(design)")
tmp_op_syn.config(design, design_name + "_" + x[1])
make_file.write("all:\n")
make_file.write("\tyosys " + script_path + design_name + "_" + x[1] + ".ys\n")
if x[0] == "InnovusFloorplan":
tmp_op_fp = eval("fp1." + "InnovusFloorplan" + "(design)")
@ -59,8 +65,8 @@ def run(design, flow):
overall_tcl.write('source %s/%s_to_drc.tcl\n'%(tcl_path, design_name))
make_file.write("\tinnovus -batch -files " + script_path + "flow.tcl")
run_path = util.getRunPath(design, "Cadence")
#make_file.write("\tinnovus -batch -files " + script_path + "flow.tcl")
run_path = util.getRunPath(design, "Yosys")
os.chdir(run_path)
print(os.getcwd())
#cmd_clean = 'rm innovus.* genus.*'
@ -68,8 +74,8 @@ def run(design, flow):
#cmd_clean = 'rm -rf fv'
#subprocess.Popen(cmd_clean, shell=True).wait()
cmd = 'make'
subprocess.Popen(cmd)
#subprocess.Popen(cmd, shell=True).wait()
#subprocess.Popen(cmd)
subprocess.Popen(cmd, shell=True).wait()
return 0

15
flow.py
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@ -16,25 +16,28 @@ class MyFlow(object):
self.params_drc = []
def flow(self):
op_synth = "GenusSynth"
#op_synth = "GenusSynth"
#self.ops.append((op_synth, "to_synth"))
op_synth = "YosysSynth"
self.ops.append((op_synth, "to_synth"))
op_floorplan = "InnovusFloorplan"
self.ops.append((op_floorplan, "to_floorplan"))
#self.ops.append((op_floorplan, "to_floorplan"))
self.params_fp.append(("r","1.0 0.7 0.0 0.0 0.0 0.0"))
#self.params_fp.append(("r","1.0 0.7 0.0 0.0 0.0 0.0"))
op_pdn = "InnovusPDN"
self.ops.append((op_pdn, "to_pdn"))
#self.ops.append((op_pdn, "to_pdn"))
op_place = "InnovusPlace"
self.ops.append((op_place, "to_place"))
#self.ops.append((op_place, "to_place"))
op_cts = "InnovusCTS"
#self.ops.append((op_cts, "to_cts"))
op_route = "InnovusRoute"
self.ops.append((op_route, "to_route"))
#self.ops.append((op_route, "to_route"))
op_drc = "InnovusDRC"
#self.ops.append((op_drc, "to_drc"))

View File

@ -69,7 +69,7 @@ class GenusSynth():
tcl = open(tcl_path + "/" + tcl_file + ".tcl", 'w', encoding='utf-8')
#tcl.write('set hdl_files %s\n'%(self.design.rtl_file))
tcl.write('set hdl_files %s\n'%(rtl_file))
tcl.write('set hdl_files {%s}\n'%(rtl_file))
tcl.write('set DESIGN %s\n'%(self.design.top_name))
tcl.write('set clkpin %s\n'%(self.design.clk_name))
tcl.write('set delay %d\n'%(self.design.delay))

View File

@ -5,6 +5,7 @@ import util
class YosysSynth():
def __init__(self, design):
self.params = dict()
self.design = design
def getObjHDL(self):
obj_path = util.getObjPath(self.design, "Yosys")
@ -40,16 +41,16 @@ class YosysSynth():
def config(self, design, tcl_file):
rtl_file = util.getHDL(self.design)
lib_file = util.getLib(self.design)
top_name = util.getTop(self.design)
#top_name = self.design.top_name
hdl_path = util.getHDLPath(self.design, "Yosys")
lib_path = util.getLibPath(self.design, "Yosys")
tcl_path = util.getScriptPath(self.design, "Yosys")
tcl = open(tcl_path + "/" + tcl_file + ".ys", 'w', encoding = 'utf-8')
tcl.write('read -sv %s\n'%(rtl_file)
tcl.write('hierarchy -top %s\n'%(top_name))
tcl.write('proc; opt; techmap; opt')
tcl.write('write_verilog %s\n'*(self.getObjHDL()))
tcl.write('read -sv %s\n'%(hdl_path + "/" + rtl_file))
tcl.write('hierarchy -top %s\n'%(self.design.top_name))
tcl.write('proc; opt; techmap; opt\n')
tcl.write('write_verilog %s\n'%(self.getObjHDL()))
tcl.close()

26
util.py
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@ -19,48 +19,48 @@ def getMmmc(design):
def getHDLPath(design, baseflow):
if baseflow == "Cadence":
hdl_path = home_path + "/design/" + design.top_name + "/hdl"
elif baseflow == "Openroad":
hdl_path = "/OpenROAD-flow/flow/designs/design/" + design.top_name + "/hdl"
elif baseflow == "Yosys":
hdl_path = home_path + "/design/" + design.top_name + "/hdl"
return hdl_path
def getLibPath(design, baseflow):
if baseflow == "Cadence":
lib_path = home_path + "/design/lib"
elif baseflow == "Openroad":
lib_path = "/OpenROAD-flow/flow/platforms/" + design.lib_name
elif baseflow == "Yosys":
lib_path = home_path + "/design/lib"
return lib_path
def getLefPath(design, baseflow):
if baseflow == "Cadence":
lef_path = home_path + "/design/lib"
elif baseflow == "Openroad":
elif baseflow == "Yosys":
lef_path = ""
return lef_path
def getRptPath(design, baseflow):
if baseflow == "Cadence":
rpt_path = home_path + "/design/" + design.top_name + "/" + design.lib_name + "/reports"
elif baseflow == "Openroad":
rpt_path = "/OpenROAD-flow/flow" + design.top_name + "/" + design.lib_name + "/reports"
elif baseflow == "Yosys":
rpt_path = home_path + "/design/" + design.top_name + "/" + design.lib_name + "/reports"
return rpt_path
def getObjPath(design, baseflow):
if baseflow == "Cadence":
obj_path = home_path + "/design/" + design.top_name + "/" + design.lib_name + "/objects"
elif baseflow == "Openroad":
obj_path = "/OpenROAD-flow/flow" + design.top_name + "/" + design.lib_name + "/objects"
elif baseflow == "Yosys":
obj_path = home_path + "/design/" + design.top_name + "/" + design.lib_name + "/objects"
return obj_path
def getScriptPath(design, baseflow):
if baseflow == "Cadence":
script_path = home_path + "/design/" + design.top_name + "/" + design.lib_name + "/scripts"
elif baseflow == "Openroad":
script_path = "/OpenROAD-flow/flow" + design.top_name + "/" + design.lib_name + "/scripts"
elif baseflow == "Yosys":
script_path = home_path + "/design/" + design.top_name + "/" + design.lib_name + "/scripts"
return script_path
def getRunPath(design, baseflow):
if baseflow == "Cadence":
run_path = home_path + "/design/" + design.top_name + "/" + design.lib_name + "/run"
elif baseflow == "Openroad":
run_path = "/OpenROAD-flow/flow" + design.top_name + "/" + design.lib_name + "/run"
elif baseflow == "Yosys":
run_path = home_path + "/design/" + design.top_name + "/" + design.lib_name + "/run"
return run_path