fix bugs; demo test
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// Generated by Cadence Genus(TM) Synthesis Solution 19.12-s121_1
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// Generated on: Aug 10 2020 11:16:47 CST (Aug 10 2020 03:16:47 UTC)
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// Verification Directory fv/gcd
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module RegRst_0x9f365fdf6c8998a(clk, in_, out, reset);
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input [0:0] clk, reset;
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input [1:0] in_;
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output [1:0] out;
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wire [0:0] clk, reset;
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wire [1:0] in_;
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wire [1:0] out;
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wire n_19, n_22;
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CDN_flop \out_reg[0] (.clk (clk), .d (n_19), .sena (1'b1), .aclr
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(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[0]));
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CDN_flop \out_reg[1] (.clk (clk), .d (n_22), .sena (1'b1), .aclr
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(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[1]));
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and g9 (n_19, in_[0], wc);
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not gc (wc, reset);
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and g10 (n_22, in_[1], wc0);
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not gc0 (wc0, reset);
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endmodule
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module lt_unsigned_rtlopto_model_20(A, B, Z);
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input [15:0] A, B;
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output Z;
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wire [15:0] A, B;
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wire Z;
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wire n_68, n_71, n_72, n_74, n_75, n_76, n_77, n_78;
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wire n_79, n_81, n_82, n_83, n_84, n_85, n_87, n_88;
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wire n_89, n_90, n_91, n_93, n_94, n_95, n_96, n_97;
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wire n_99, n_100, n_101, n_102, n_103, n_105, n_106, n_107;
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wire n_108, n_109, n_111, n_112, n_113, n_114, n_115, n_117;
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wire n_118, n_121, n_122, n_123, n_124, n_127, n_129, n_131;
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wire n_132, n_134, n_137, n_139, n_141, n_142, n_144, n_147;
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wire n_149, n_151, n_152, n_154, n_162, n_164, n_165, n_166;
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wire n_169, n_177, n_178, n_179, n_181, n_200, n_201, n_202;
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not g18 (Z, n_68);
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nand g55 (n_118, n_74, n_75);
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nor g56 (n_79, n_76, n_77);
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nor g59 (n_121, n_81, n_77);
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nor g60 (n_85, n_82, n_83);
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nor g63 (n_127, n_87, n_83);
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nor g64 (n_91, n_88, n_89);
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nor g67 (n_129, n_93, n_89);
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nor g68 (n_97, n_94, n_95);
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nor g71 (n_137, n_99, n_95);
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nor g72 (n_103, n_100, n_101);
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nor g75 (n_139, n_105, n_101);
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nor g76 (n_109, n_106, n_107);
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nor g79 (n_147, n_111, n_107);
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nor g80 (n_115, n_112, n_113);
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nor g83 (n_149, n_117, n_113);
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nand g87 (n_123, n_121, n_118);
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nand g88 (n_154, n_122, n_123);
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nand g98 (n_162, n_127, n_129);
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nand g108 (n_169, n_137, n_139);
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nand g118 (n_177, n_147, n_149);
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nand g129 (n_181, n_164, n_165);
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nor g143 (n_179, n_177, n_166);
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nor g146 (n_200, n_169, n_177);
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nand g164 (n_202, n_200, n_181);
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nand g165 (n_68, n_201, n_202);
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and g207 (n_111, B[12], wc1);
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not gc1 (wc1, A[12]);
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and g208 (n_107, B[13], wc2);
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not gc2 (wc2, A[13]);
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and g209 (n_117, B[14], wc3);
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not gc3 (wc3, A[14]);
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and g210 (n_113, B[15], wc4);
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not gc4 (wc4, A[15]);
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or g211 (n_94, B[8], wc5);
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not gc5 (wc5, A[8]);
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and g212 (n_95, B[9], wc6);
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not gc6 (wc6, A[9]);
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or g213 (n_96, B[9], wc7);
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not gc7 (wc7, A[9]);
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and g214 (n_105, B[10], wc8);
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not gc8 (wc8, A[10]);
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and g215 (n_101, B[11], wc9);
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not gc9 (wc9, A[11]);
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or g216 (n_100, B[10], wc10);
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not gc10 (wc10, A[10]);
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or g217 (n_102, B[11], wc11);
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not gc11 (wc11, A[11]);
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or g218 (n_106, B[12], wc12);
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not gc12 (wc12, A[12]);
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or g219 (n_108, B[13], wc13);
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not gc13 (wc13, A[13]);
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or g220 (n_112, B[14], wc14);
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not gc14 (wc14, A[14]);
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or g221 (n_114, B[15], wc15);
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not gc15 (wc15, A[15]);
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and g222 (n_99, B[8], wc16);
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not gc16 (wc16, A[8]);
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or g223 (n_82, B[4], wc17);
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not gc17 (wc17, A[4]);
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and g224 (n_83, B[5], wc18);
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not gc18 (wc18, A[5]);
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or g225 (n_84, B[5], wc19);
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not gc19 (wc19, A[5]);
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and g226 (n_93, B[6], wc20);
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not gc20 (wc20, A[6]);
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and g227 (n_89, B[7], wc21);
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not gc21 (wc21, A[7]);
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or g228 (n_88, B[6], wc22);
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not gc22 (wc22, A[6]);
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or g229 (n_90, B[7], wc23);
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not gc23 (wc23, A[7]);
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or g230 (n_76, B[2], wc24);
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not gc24 (wc24, A[2]);
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and g231 (n_77, B[3], wc25);
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not gc25 (wc25, A[3]);
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or g232 (n_78, B[3], wc26);
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not gc26 (wc26, A[3]);
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and g233 (n_81, B[2], wc27);
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not gc27 (wc27, A[2]);
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or g234 (n_74, B[1], wc28);
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not gc28 (wc28, A[1]);
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or g235 (n_72, wc29, A[0]);
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not gc29 (wc29, B[0]);
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and g236 (n_71, B[1], wc30);
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not gc30 (wc30, A[1]);
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and g237 (n_87, B[4], wc31);
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not gc31 (wc31, A[4]);
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and g238 (n_134, n_96, wc32);
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not gc32 (wc32, n_97);
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and g239 (n_141, n_102, wc33);
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not gc33 (wc33, n_103);
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and g240 (n_144, n_108, wc34);
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not gc34 (wc34, n_109);
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and g241 (n_151, n_114, wc35);
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not gc35 (wc35, n_115);
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and g242 (n_124, n_84, wc36);
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not gc36 (wc36, n_85);
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and g243 (n_131, n_90, wc37);
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not gc37 (wc37, n_91);
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and g244 (n_122, n_78, wc38);
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not gc38 (wc38, n_79);
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or g245 (n_75, n_71, wc39);
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not gc39 (wc39, n_72);
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and g246 (n_142, wc40, n_139);
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not gc40 (wc40, n_134);
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and g247 (n_152, wc41, n_149);
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not gc41 (wc41, n_144);
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and g248 (n_132, wc42, n_129);
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not gc42 (wc42, n_124);
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and g249 (n_166, wc43, n_141);
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not gc43 (wc43, n_142);
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and g250 (n_178, wc44, n_151);
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not gc44 (wc44, n_152);
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and g251 (n_164, wc45, n_131);
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not gc45 (wc45, n_132);
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and g252 (n_201, n_178, wc46);
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not gc46 (wc46, n_179);
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or g253 (n_165, n_162, wc47);
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not gc47 (wc47, n_154);
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endmodule
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module RegEn_0x68db79c4ec1d6e5b(clk, en, in_, out, reset);
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input [0:0] clk, en, reset;
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input [15:0] in_;
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output [15:0] out;
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wire [0:0] clk, en, reset;
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wire [15:0] in_;
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wire [15:0] out;
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wire n_98, n_99, n_101, n_103, n_105, n_107, n_109, n_111;
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wire n_113, n_115, n_117, n_119, n_121, n_123, n_125, n_127;
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wire n_129;
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CDN_flop \out_reg[0] (.clk (clk), .d (n_99), .sena (1'b1), .aclr
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(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[0]));
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CDN_flop \out_reg[1] (.clk (clk), .d (n_101), .sena (1'b1), .aclr
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(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[1]));
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CDN_flop \out_reg[2] (.clk (clk), .d (n_103), .sena (1'b1), .aclr
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(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[2]));
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CDN_flop \out_reg[3] (.clk (clk), .d (n_105), .sena (1'b1), .aclr
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(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[3]));
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CDN_flop \out_reg[4] (.clk (clk), .d (n_107), .sena (1'b1), .aclr
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(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[4]));
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CDN_flop \out_reg[5] (.clk (clk), .d (n_109), .sena (1'b1), .aclr
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(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[5]));
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CDN_flop \out_reg[6] (.clk (clk), .d (n_111), .sena (1'b1), .aclr
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(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[6]));
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CDN_flop \out_reg[7] (.clk (clk), .d (n_113), .sena (1'b1), .aclr
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(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[7]));
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CDN_flop \out_reg[8] (.clk (clk), .d (n_115), .sena (1'b1), .aclr
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(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[8]));
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CDN_flop \out_reg[9] (.clk (clk), .d (n_117), .sena (1'b1), .aclr
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(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[9]));
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CDN_flop \out_reg[10] (.clk (clk), .d (n_119), .sena (1'b1), .aclr
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(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[10]));
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CDN_flop \out_reg[11] (.clk (clk), .d (n_121), .sena (1'b1), .aclr
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(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[11]));
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CDN_flop \out_reg[12] (.clk (clk), .d (n_123), .sena (1'b1), .aclr
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(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[12]));
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CDN_flop \out_reg[13] (.clk (clk), .d (n_125), .sena (1'b1), .aclr
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(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[13]));
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CDN_flop \out_reg[14] (.clk (clk), .d (n_127), .sena (1'b1), .aclr
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(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[14]));
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CDN_flop \out_reg[15] (.clk (clk), .d (n_129), .sena (1'b1), .aclr
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(1'b0), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (out[15]));
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not g18 (n_98, en);
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CDN_mux2 g19_g1(.sel0 (n_98), .data0 (out[0]), .sel1 (en), .data1
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(in_[0]), .z (n_99));
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CDN_mux2 g21_g1(.sel0 (n_98), .data0 (out[1]), .sel1 (en), .data1
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(in_[1]), .z (n_101));
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CDN_mux2 g23_g1(.sel0 (n_98), .data0 (out[2]), .sel1 (en), .data1
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(in_[2]), .z (n_103));
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CDN_mux2 g25_g1(.sel0 (n_98), .data0 (out[3]), .sel1 (en), .data1
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(in_[3]), .z (n_105));
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CDN_mux2 g27_g1(.sel0 (n_98), .data0 (out[4]), .sel1 (en), .data1
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(in_[4]), .z (n_107));
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CDN_mux2 g29_g1(.sel0 (n_98), .data0 (out[5]), .sel1 (en), .data1
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(in_[5]), .z (n_109));
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CDN_mux2 g31_g1(.sel0 (n_98), .data0 (out[6]), .sel1 (en), .data1
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(in_[6]), .z (n_111));
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CDN_mux2 g33_g1(.sel0 (n_98), .data0 (out[7]), .sel1 (en), .data1
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(in_[7]), .z (n_113));
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CDN_mux2 g35_g1(.sel0 (n_98), .data0 (out[8]), .sel1 (en), .data1
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(in_[8]), .z (n_115));
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CDN_mux2 g37_g1(.sel0 (n_98), .data0 (out[9]), .sel1 (en), .data1
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(in_[9]), .z (n_117));
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CDN_mux2 g39_g1(.sel0 (n_98), .data0 (out[10]), .sel1 (en), .data1
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(in_[10]), .z (n_119));
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CDN_mux2 g41_g1(.sel0 (n_98), .data0 (out[11]), .sel1 (en), .data1
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(in_[11]), .z (n_121));
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CDN_mux2 g43_g1(.sel0 (n_98), .data0 (out[12]), .sel1 (en), .data1
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(in_[12]), .z (n_123));
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CDN_mux2 g45_g1(.sel0 (n_98), .data0 (out[13]), .sel1 (en), .data1
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(in_[13]), .z (n_125));
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CDN_mux2 g47_g1(.sel0 (n_98), .data0 (out[14]), .sel1 (en), .data1
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(in_[14]), .z (n_127));
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CDN_mux2 g49_g1(.sel0 (n_98), .data0 (out[15]), .sel1 (en), .data1
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(in_[15]), .z (n_129));
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endmodule
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module Mux_0xdd6473406d1a99a(clk, in_$000, in_$001, out, reset, sel);
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input [0:0] clk, reset, sel;
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input [15:0] in_$000, in_$001;
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output [15:0] out;
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wire [0:0] clk, reset, sel;
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wire [15:0] in_$000, in_$001;
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wire [15:0] out;
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CDN_bmux2 \mux_in_[sel]_721_11_g1 (.sel0 (sel), .data0 (in_$000[15]),
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.data1 (in_$001[15]), .z (out[15]));
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CDN_bmux2 \mux_in_[sel]_721_11_g2 (.sel0 (sel), .data0 (in_$000[14]),
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.data1 (in_$001[14]), .z (out[14]));
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CDN_bmux2 \mux_in_[sel]_721_11_g3 (.sel0 (sel), .data0 (in_$000[13]),
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.data1 (in_$001[13]), .z (out[13]));
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CDN_bmux2 \mux_in_[sel]_721_11_g4 (.sel0 (sel), .data0 (in_$000[12]),
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.data1 (in_$001[12]), .z (out[12]));
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CDN_bmux2 \mux_in_[sel]_721_11_g5 (.sel0 (sel), .data0 (in_$000[11]),
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.data1 (in_$001[11]), .z (out[11]));
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CDN_bmux2 \mux_in_[sel]_721_11_g6 (.sel0 (sel), .data0 (in_$000[10]),
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.data1 (in_$001[10]), .z (out[10]));
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CDN_bmux2 \mux_in_[sel]_721_11_g7 (.sel0 (sel), .data0 (in_$000[9]),
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.data1 (in_$001[9]), .z (out[9]));
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CDN_bmux2 \mux_in_[sel]_721_11_g8 (.sel0 (sel), .data0 (in_$000[8]),
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.data1 (in_$001[8]), .z (out[8]));
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CDN_bmux2 \mux_in_[sel]_721_11_g9 (.sel0 (sel), .data0 (in_$000[7]),
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.data1 (in_$001[7]), .z (out[7]));
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CDN_bmux2 \mux_in_[sel]_721_11_g10 (.sel0 (sel), .data0 (in_$000[6]),
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.data1 (in_$001[6]), .z (out[6]));
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CDN_bmux2 \mux_in_[sel]_721_11_g11 (.sel0 (sel), .data0 (in_$000[5]),
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.data1 (in_$001[5]), .z (out[5]));
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CDN_bmux2 \mux_in_[sel]_721_11_g12 (.sel0 (sel), .data0 (in_$000[4]),
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.data1 (in_$001[4]), .z (out[4]));
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CDN_bmux2 \mux_in_[sel]_721_11_g13 (.sel0 (sel), .data0 (in_$000[3]),
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.data1 (in_$001[3]), .z (out[3]));
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CDN_bmux2 \mux_in_[sel]_721_11_g14 (.sel0 (sel), .data0 (in_$000[2]),
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.data1 (in_$001[2]), .z (out[2]));
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CDN_bmux2 \mux_in_[sel]_721_11_g15 (.sel0 (sel), .data0 (in_$000[1]),
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.data1 (in_$001[1]), .z (out[1]));
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CDN_bmux2 \mux_in_[sel]_721_11_g16 (.sel0 (sel), .data0 (in_$000[0]),
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.data1 (in_$001[0]), .z (out[0]));
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endmodule
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module ZeroComparator_0x422b1f52edd46a85(clk, in_, out, reset);
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input [0:0] clk, reset;
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input [15:0] in_;
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||||
output [0:0] out;
|
||||
wire [0:0] clk, reset;
|
||||
wire [15:0] in_;
|
||||
wire [0:0] out;
|
||||
wire n_20, n_21, n_22, n_23, n_24, n_26;
|
||||
xnor g1 (n_26, in_[0], 1'b0);
|
||||
nor g2 (n_20, in_[15], in_[14], in_[13], in_[12]);
|
||||
nor g3 (n_21, in_[11], in_[10], in_[9], in_[8]);
|
||||
nor g4 (n_22, in_[7], in_[6], in_[5], in_[4]);
|
||||
nor g5 (n_23, in_[3], in_[2], in_[1]);
|
||||
nand g6 (n_24, n_26, n_20, n_21, n_22);
|
||||
and g9 (out, wc48, n_23);
|
||||
not gc48 (wc48, n_24);
|
||||
endmodule
|
||||
|
||||
module sub_unsigned(A, B, Z);
|
||||
input [15:0] A, B;
|
||||
output [15:0] Z;
|
||||
wire [15:0] A, B;
|
||||
wire [15:0] Z;
|
||||
wire n_51, n_52, n_53, n_54, n_55, n_56, n_57, n_58;
|
||||
wire n_59, n_60, n_61, n_62, n_63, n_64, n_65, n_66;
|
||||
wire n_69, n_71, n_72, n_73, n_74, n_75, n_76, n_77;
|
||||
wire n_78, n_79, n_80, n_81, n_82, n_83, n_84, n_85;
|
||||
wire n_86, n_87, n_88, n_89, n_90, n_91, n_92, n_93;
|
||||
wire n_94, n_95, n_96, n_97, n_98, n_99, n_100, n_101;
|
||||
wire n_102, n_103, n_104, n_105, n_106, n_107, n_108, n_109;
|
||||
wire n_110, n_111, n_112, n_113, n_114, n_117, n_118, n_119;
|
||||
wire n_120, n_121, n_122, n_123, n_124, n_125, n_126, n_127;
|
||||
wire n_128, n_129, n_130, n_131, n_132, n_133, n_134, n_135;
|
||||
wire n_136, n_137, n_138, n_139, n_140, n_141, n_142, n_143;
|
||||
wire n_144, n_145, n_146, n_147, n_148, n_154, n_155, n_156;
|
||||
wire n_157, n_158, n_159, n_160, n_161, n_162, n_163, n_164;
|
||||
wire n_165, n_166, n_167, n_168, n_169, n_170, n_171, n_172;
|
||||
wire n_173, n_174, n_175, n_176, n_181, n_182, n_183, n_184;
|
||||
wire n_185, n_186, n_187, n_188, n_189, n_190, n_191, n_192;
|
||||
wire n_193, n_194, n_195, n_196, n_197, n_198, n_199, n_203;
|
||||
wire n_204, n_205, n_206, n_207, n_208, n_209, n_210, n_211;
|
||||
wire n_212, n_213, n_214, n_215, n_216, n_217, n_218, n_219;
|
||||
wire n_220, n_221, n_222, n_223, n_224, n_225, n_226, n_227;
|
||||
wire n_228, n_229, n_230, n_231, n_232, n_233, n_234, n_235;
|
||||
wire n_236, n_237;
|
||||
not g2 (n_51, B[15]);
|
||||
not g3 (n_52, B[14]);
|
||||
not g4 (n_53, B[13]);
|
||||
not g5 (n_54, B[12]);
|
||||
not g6 (n_55, B[11]);
|
||||
not g7 (n_56, B[10]);
|
||||
not g8 (n_57, B[9]);
|
||||
not g9 (n_58, B[8]);
|
||||
not g10 (n_59, B[7]);
|
||||
not g11 (n_60, B[6]);
|
||||
not g12 (n_61, B[5]);
|
||||
not g13 (n_62, B[4]);
|
||||
not g14 (n_63, B[3]);
|
||||
not g15 (n_64, B[2]);
|
||||
not g16 (n_65, B[1]);
|
||||
not g17 (n_66, B[0]);
|
||||
xor g19 (n_237, A[0], n_66);
|
||||
nand g22 (n_72, n_69, B[0]);
|
||||
nor g23 (n_71, A[1], n_65);
|
||||
nand g24 (n_74, A[1], n_65);
|
||||
nor g25 (n_81, A[2], n_64);
|
||||
nand g26 (n_76, A[2], n_64);
|
||||
nor g27 (n_77, A[3], n_63);
|
||||
nand g28 (n_78, A[3], n_63);
|
||||
nor g29 (n_87, A[4], n_62);
|
||||
nand g30 (n_82, A[4], n_62);
|
||||
nor g31 (n_83, A[5], n_61);
|
||||
nand g32 (n_84, A[5], n_61);
|
||||
nor g33 (n_93, A[6], n_60);
|
||||
nand g34 (n_88, A[6], n_60);
|
||||
nor g35 (n_89, A[7], n_59);
|
||||
nand g36 (n_90, A[7], n_59);
|
||||
nor g37 (n_99, A[8], n_58);
|
||||
nand g38 (n_94, A[8], n_58);
|
||||
nor g39 (n_95, A[9], n_57);
|
||||
nand g40 (n_96, A[9], n_57);
|
||||
nor g41 (n_105, A[10], n_56);
|
||||
nand g42 (n_100, A[10], n_56);
|
||||
nor g43 (n_101, A[11], n_55);
|
||||
nand g44 (n_102, A[11], n_55);
|
||||
nor g45 (n_111, A[12], n_54);
|
||||
nand g46 (n_106, A[12], n_54);
|
||||
nor g47 (n_107, A[13], n_53);
|
||||
nand g48 (n_108, A[13], n_53);
|
||||
nor g49 (n_117, A[14], n_52);
|
||||
nand g50 (n_112, A[14], n_52);
|
||||
nor g51 (n_113, A[15], n_51);
|
||||
nand g52 (n_114, A[15], n_51);
|
||||
not g53 (n_73, n_71);
|
||||
nand g54 (n_75, n_72, n_73);
|
||||
nand g55 (n_118, n_74, n_75);
|
||||
nor g56 (n_79, n_76, n_77);
|
||||
not g57 (n_80, n_78);
|
||||
nor g58 (n_122, n_79, n_80);
|
||||
nor g59 (n_121, n_81, n_77);
|
||||
nor g60 (n_85, n_82, n_83);
|
||||
not g61 (n_86, n_84);
|
||||
nor g62 (n_124, n_85, n_86);
|
||||
nor g63 (n_127, n_87, n_83);
|
||||
nor g64 (n_91, n_88, n_89);
|
||||
not g65 (n_92, n_90);
|
||||
nor g66 (n_131, n_91, n_92);
|
||||
nor g67 (n_129, n_93, n_89);
|
||||
nor g68 (n_97, n_94, n_95);
|
||||
not g69 (n_98, n_96);
|
||||
nor g70 (n_134, n_97, n_98);
|
||||
nor g71 (n_137, n_99, n_95);
|
||||
nor g72 (n_103, n_100, n_101);
|
||||
not g73 (n_104, n_102);
|
||||
nor g74 (n_141, n_103, n_104);
|
||||
nor g75 (n_139, n_105, n_101);
|
||||
nor g76 (n_109, n_106, n_107);
|
||||
not g77 (n_110, n_108);
|
||||
nor g78 (n_144, n_109, n_110);
|
||||
nor g79 (n_147, n_111, n_107);
|
||||
not g84 (n_119, n_81);
|
||||
nand g85 (n_120, n_118, n_119);
|
||||
nand g86 (n_206, n_76, n_120);
|
||||
nand g87 (n_123, n_121, n_118);
|
||||
nand g88 (n_154, n_122, n_123);
|
||||
nor g89 (n_125, n_93, n_124);
|
||||
not g90 (n_126, n_88);
|
||||
nor g91 (n_160, n_125, n_126);
|
||||
not g92 (n_128, n_93);
|
||||
nand g93 (n_158, n_127, n_128);
|
||||
not g94 (n_130, n_129);
|
||||
nor g95 (n_132, n_124, n_130);
|
||||
not g96 (n_133, n_131);
|
||||
nor g97 (n_164, n_132, n_133);
|
||||
nand g98 (n_162, n_127, n_129);
|
||||
nor g99 (n_135, n_105, n_134);
|
||||
not g100 (n_136, n_100);
|
||||
nor g101 (n_187, n_135, n_136);
|
||||
not g102 (n_138, n_105);
|
||||
nand g103 (n_185, n_137, n_138);
|
||||
not g104 (n_140, n_139);
|
||||
nor g105 (n_142, n_134, n_140);
|
||||
not g106 (n_143, n_141);
|
||||
nor g107 (n_166, n_142, n_143);
|
||||
nand g108 (n_169, n_137, n_139);
|
||||
nor g109 (n_145, n_117, n_144);
|
||||
not g110 (n_146, n_112);
|
||||
nor g111 (n_174, n_145, n_146);
|
||||
not g112 (n_148, n_117);
|
||||
nand g113 (n_173, n_147, n_148);
|
||||
not g119 (n_155, n_87);
|
||||
nand g120 (n_156, n_154, n_155);
|
||||
nand g121 (n_210, n_82, n_156);
|
||||
nand g122 (n_157, n_127, n_154);
|
||||
nand g123 (n_212, n_124, n_157);
|
||||
not g124 (n_159, n_158);
|
||||
nand g125 (n_161, n_154, n_159);
|
||||
nand g126 (n_215, n_160, n_161);
|
||||
not g127 (n_163, n_162);
|
||||
nand g128 (n_165, n_154, n_163);
|
||||
nand g129 (n_181, n_164, n_165);
|
||||
nor g130 (n_167, n_111, n_166);
|
||||
not g131 (n_168, n_106);
|
||||
nor g132 (n_192, n_167, n_168);
|
||||
nor g133 (n_191, n_111, n_169);
|
||||
not g134 (n_170, n_147);
|
||||
nor g135 (n_171, n_166, n_170);
|
||||
not g136 (n_172, n_144);
|
||||
nor g137 (n_195, n_171, n_172);
|
||||
nor g138 (n_194, n_169, n_170);
|
||||
nor g139 (n_175, n_173, n_166);
|
||||
not g140 (n_176, n_174);
|
||||
nor g141 (n_198, n_175, n_176);
|
||||
nor g142 (n_197, n_169, n_173);
|
||||
not g147 (n_182, n_99);
|
||||
nand g148 (n_183, n_181, n_182);
|
||||
nand g149 (n_219, n_94, n_183);
|
||||
nand g150 (n_184, n_137, n_181);
|
||||
nand g151 (n_221, n_134, n_184);
|
||||
not g152 (n_186, n_185);
|
||||
nand g153 (n_188, n_181, n_186);
|
||||
nand g154 (n_224, n_187, n_188);
|
||||
not g155 (n_189, n_169);
|
||||
nand g156 (n_190, n_181, n_189);
|
||||
nand g157 (n_227, n_166, n_190);
|
||||
nand g158 (n_193, n_191, n_181);
|
||||
nand g159 (n_230, n_192, n_193);
|
||||
nand g160 (n_196, n_194, n_181);
|
||||
nand g161 (n_232, n_195, n_196);
|
||||
nand g162 (n_199, n_197, n_181);
|
||||
nand g163 (n_235, n_198, n_199);
|
||||
nand g166 (n_203, n_73, n_74);
|
||||
xnor g167 (Z[1], n_72, n_203);
|
||||
nand g168 (n_204, n_119, n_76);
|
||||
xnor g169 (Z[2], n_118, n_204);
|
||||
not g170 (n_205, n_77);
|
||||
nand g171 (n_207, n_205, n_78);
|
||||
xnor g172 (Z[3], n_206, n_207);
|
||||
nand g173 (n_208, n_155, n_82);
|
||||
xnor g174 (Z[4], n_154, n_208);
|
||||
not g175 (n_209, n_83);
|
||||
nand g176 (n_211, n_209, n_84);
|
||||
xnor g177 (Z[5], n_210, n_211);
|
||||
nand g178 (n_213, n_128, n_88);
|
||||
xnor g179 (Z[6], n_212, n_213);
|
||||
not g180 (n_214, n_89);
|
||||
nand g181 (n_216, n_214, n_90);
|
||||
xnor g182 (Z[7], n_215, n_216);
|
||||
nand g183 (n_217, n_182, n_94);
|
||||
xnor g184 (Z[8], n_181, n_217);
|
||||
not g185 (n_218, n_95);
|
||||
nand g186 (n_220, n_218, n_96);
|
||||
xnor g187 (Z[9], n_219, n_220);
|
||||
nand g188 (n_222, n_138, n_100);
|
||||
xnor g189 (Z[10], n_221, n_222);
|
||||
not g190 (n_223, n_101);
|
||||
nand g191 (n_225, n_223, n_102);
|
||||
xnor g192 (Z[11], n_224, n_225);
|
||||
not g193 (n_226, n_111);
|
||||
nand g194 (n_228, n_226, n_106);
|
||||
xnor g195 (Z[12], n_227, n_228);
|
||||
not g196 (n_229, n_107);
|
||||
nand g197 (n_231, n_229, n_108);
|
||||
xnor g198 (Z[13], n_230, n_231);
|
||||
nand g199 (n_233, n_148, n_112);
|
||||
xnor g200 (Z[14], n_232, n_233);
|
||||
not g201 (n_234, n_113);
|
||||
nand g202 (n_236, n_234, n_114);
|
||||
xnor g203 (Z[15], n_235, n_236);
|
||||
not g205 (n_69, A[0]);
|
||||
not g206 (Z[0], n_237);
|
||||
endmodule
|
||||
|
||||
module gcd(clk, req_msg, req_rdy, req_val, reset, resp_msg, resp_rdy,
|
||||
resp_val);
|
||||
input clk, req_val, reset, resp_rdy;
|
||||
input [31:0] req_msg;
|
||||
output req_rdy, resp_val;
|
||||
output [15:0] resp_msg;
|
||||
wire clk, req_val, reset, resp_rdy;
|
||||
wire [31:0] req_msg;
|
||||
wire req_rdy, resp_val;
|
||||
wire [15:0] resp_msg;
|
||||
wire [1:0] ctrl_state$in_;
|
||||
wire [1:0] ctrl_state$out;
|
||||
wire [15:0] dpath_a_reg$out;
|
||||
wire [15:0] dpath_b_reg$out;
|
||||
wire [0:0] ctrl$a_reg_en;
|
||||
wire [15:0] dpath_a_mux$out;
|
||||
wire [15:0] dpath_b_mux$out;
|
||||
wire [0:0] ctrl$b_reg_en;
|
||||
wire [0:0] dpath$is_b_zero;
|
||||
wire n_2, n_7, n_39, n_45, n_51, n_57, n_63, n_69;
|
||||
wire n_75, n_81, n_87, n_93, n_94, n_99, n_102, n_103;
|
||||
wire n_105, n_108, n_109, n_110, n_111, n_112, n_476, n_477;
|
||||
wire n_478, n_479, n_480, n_481, n_482, n_483, n_484, n_485;
|
||||
RegRst_0x9f365fdf6c8998a ctrl_state(.clk (clk), .in_
|
||||
(ctrl_state$in_), .out (ctrl_state$out), .reset (reset));
|
||||
lt_unsigned_rtlopto_model_20 dpath_a_lt_b_lt_607_16(.A
|
||||
(dpath_a_reg$out), .B (dpath_b_reg$out), .Z (n_94));
|
||||
RegEn_0x68db79c4ec1d6e5b dpath_a_reg(.clk (clk), .en (ctrl$a_reg_en),
|
||||
.in_ (dpath_a_mux$out), .out (dpath_a_reg$out), .reset (1'b0));
|
||||
Mux_0xdd6473406d1a99a dpath_b_mux(.clk (1'b0), .in_$000
|
||||
(dpath_a_reg$out), .in_$001 (req_msg[15:0]), .out
|
||||
(dpath_b_mux$out), .reset (1'b0), .sel (req_rdy));
|
||||
RegEn_0x68db79c4ec1d6e5b dpath_b_reg(.clk (clk), .en (ctrl$b_reg_en),
|
||||
.in_ (dpath_b_mux$out), .out (dpath_b_reg$out), .reset (1'b0));
|
||||
ZeroComparator_0x422b1f52edd46a85 dpath_b_zero(.clk (1'b0), .in_
|
||||
(dpath_b_reg$out), .out (dpath$is_b_zero), .reset (1'b0));
|
||||
sub_unsigned dpath_sub_sub_752_15(.A (dpath_a_reg$out), .B
|
||||
(dpath_b_reg$out), .Z (resp_msg));
|
||||
CDN_bmux4 ctrl_mux_b_reg_en_279_10_g1(.sel0 (ctrl_state$out[0]),
|
||||
.data0 (1'b1), .data1 (n_94), .sel1 (ctrl_state$out[1]), .data2
|
||||
(1'b0), .data3 (1'b0), .z (ctrl$b_reg_en));
|
||||
not g4 (ctrl$a_reg_en[0], ctrl_state$out[1]);
|
||||
nor g22 (req_rdy, ctrl_state$out[0], ctrl_state$out[1]);
|
||||
nor g219 (resp_val, ctrl$a_reg_en[0], ctrl_state$out[0]);
|
||||
not g1 (n_2, ctrl_state$out[0]);
|
||||
or g2 (n_7, n_2, ctrl_state$out[1]);
|
||||
CDN_bmux2 g3(.sel0 (n_94), .data0 (n_476), .data1 (n_477), .z
|
||||
(dpath_a_mux$out[0]));
|
||||
CDN_bmux2 g6(.sel0 (n_94), .data0 (n_478), .data1 (n_479), .z
|
||||
(dpath_a_mux$out[1]));
|
||||
CDN_bmux2 g9(.sel0 (n_94), .data0 (n_480), .data1 (n_481), .z
|
||||
(dpath_a_mux$out[2]));
|
||||
CDN_bmux2 g12(.sel0 (n_94), .data0 (n_482), .data1 (n_483), .z
|
||||
(dpath_a_mux$out[3]));
|
||||
CDN_bmux2 g15(.sel0 (n_94), .data0 (n_484), .data1 (n_485), .z
|
||||
(dpath_a_mux$out[4]));
|
||||
CDN_bmux2 g18(.sel0 (n_94), .data0 (resp_msg[5]), .data1
|
||||
(dpath_b_reg$out[5]), .z (n_39));
|
||||
CDN_bmux2 g19(.sel0 (n_7), .data0 (n_39), .data1 (req_msg[21]), .z
|
||||
(dpath_a_mux$out[5]));
|
||||
CDN_bmux2 g21(.sel0 (n_94), .data0 (resp_msg[6]), .data1
|
||||
(dpath_b_reg$out[6]), .z (n_45));
|
||||
CDN_bmux2 g221(.sel0 (n_7), .data0 (n_45), .data1 (req_msg[22]), .z
|
||||
(dpath_a_mux$out[6]));
|
||||
CDN_bmux2 g24(.sel0 (n_94), .data0 (resp_msg[7]), .data1
|
||||
(dpath_b_reg$out[7]), .z (n_51));
|
||||
CDN_bmux2 g25(.sel0 (n_7), .data0 (n_51), .data1 (req_msg[23]), .z
|
||||
(dpath_a_mux$out[7]));
|
||||
CDN_bmux2 g27(.sel0 (n_94), .data0 (resp_msg[8]), .data1
|
||||
(dpath_b_reg$out[8]), .z (n_57));
|
||||
CDN_bmux2 g28(.sel0 (n_7), .data0 (n_57), .data1 (req_msg[24]), .z
|
||||
(dpath_a_mux$out[8]));
|
||||
CDN_bmux2 g30(.sel0 (n_94), .data0 (resp_msg[9]), .data1
|
||||
(dpath_b_reg$out[9]), .z (n_63));
|
||||
CDN_bmux2 g31(.sel0 (n_7), .data0 (n_63), .data1 (req_msg[25]), .z
|
||||
(dpath_a_mux$out[9]));
|
||||
CDN_bmux2 g33(.sel0 (n_94), .data0 (resp_msg[10]), .data1
|
||||
(dpath_b_reg$out[10]), .z (n_69));
|
||||
CDN_bmux2 g34(.sel0 (n_7), .data0 (n_69), .data1 (req_msg[26]), .z
|
||||
(dpath_a_mux$out[10]));
|
||||
CDN_bmux2 g36(.sel0 (n_94), .data0 (resp_msg[11]), .data1
|
||||
(dpath_b_reg$out[11]), .z (n_75));
|
||||
CDN_bmux2 g37(.sel0 (n_7), .data0 (n_75), .data1 (req_msg[27]), .z
|
||||
(dpath_a_mux$out[11]));
|
||||
CDN_bmux2 g39(.sel0 (n_94), .data0 (resp_msg[12]), .data1
|
||||
(dpath_b_reg$out[12]), .z (n_81));
|
||||
CDN_bmux2 g40(.sel0 (n_7), .data0 (n_81), .data1 (req_msg[28]), .z
|
||||
(dpath_a_mux$out[12]));
|
||||
CDN_bmux2 g42(.sel0 (n_94), .data0 (resp_msg[13]), .data1
|
||||
(dpath_b_reg$out[13]), .z (n_87));
|
||||
CDN_bmux2 g43(.sel0 (n_7), .data0 (n_87), .data1 (req_msg[29]), .z
|
||||
(dpath_a_mux$out[13]));
|
||||
CDN_bmux2 g45(.sel0 (n_94), .data0 (resp_msg[14]), .data1
|
||||
(dpath_b_reg$out[14]), .z (n_93));
|
||||
CDN_bmux2 g46(.sel0 (n_7), .data0 (n_93), .data1 (req_msg[30]), .z
|
||||
(dpath_a_mux$out[14]));
|
||||
CDN_bmux2 g48(.sel0 (n_94), .data0 (resp_msg[15]), .data1
|
||||
(dpath_b_reg$out[15]), .z (n_99));
|
||||
CDN_bmux2 g49(.sel0 (n_7), .data0 (n_99), .data1 (req_msg[31]), .z
|
||||
(dpath_a_mux$out[15]));
|
||||
not g50 (n_102, dpath$is_b_zero[0]);
|
||||
or g51 (n_103, n_102, n_94);
|
||||
CDN_bmux2 g52(.sel0 (ctrl_state$out[0]), .data0 (req_val), .data1
|
||||
(n_103), .z (n_105));
|
||||
CDN_bmux2 g53(.sel0 (ctrl_state$out[1]), .data0 (n_105), .data1
|
||||
(ctrl_state$out[0]), .z (ctrl_state$in_[0]));
|
||||
not g54 (n_108, resp_rdy);
|
||||
or g55 (n_109, n_108, ctrl_state$out[0]);
|
||||
and g56 (n_111, n_109, ctrl_state$out[1]);
|
||||
or g57 (n_110, n_103, n_2);
|
||||
not g58 (n_112, n_110);
|
||||
or g59 (ctrl_state$in_[1], n_111, n_112);
|
||||
CDN_bmux2 g220_dup_0(.sel0 (n_7), .data0 (resp_msg[0]), .data1
|
||||
(req_msg[16]), .z (n_476));
|
||||
CDN_bmux2 g220_dup_1(.sel0 (n_7), .data0 (dpath_b_reg$out[0]), .data1
|
||||
(req_msg[16]), .z (n_477));
|
||||
CDN_bmux2 g7_dup_0(.sel0 (n_7), .data0 (resp_msg[1]), .data1
|
||||
(req_msg[17]), .z (n_478));
|
||||
CDN_bmux2 g7_dup_1(.sel0 (n_7), .data0 (dpath_b_reg$out[1]), .data1
|
||||
(req_msg[17]), .z (n_479));
|
||||
CDN_bmux2 g10_dup_0(.sel0 (n_7), .data0 (resp_msg[2]), .data1
|
||||
(req_msg[18]), .z (n_480));
|
||||
CDN_bmux2 g10_dup_1(.sel0 (n_7), .data0 (dpath_b_reg$out[2]), .data1
|
||||
(req_msg[18]), .z (n_481));
|
||||
CDN_bmux2 g13_dup_0(.sel0 (n_7), .data0 (resp_msg[3]), .data1
|
||||
(req_msg[19]), .z (n_482));
|
||||
CDN_bmux2 g13_dup_1(.sel0 (n_7), .data0 (dpath_b_reg$out[3]), .data1
|
||||
(req_msg[19]), .z (n_483));
|
||||
CDN_bmux2 g16_dup_0(.sel0 (n_7), .data0 (resp_msg[4]), .data1
|
||||
(req_msg[20]), .z (n_484));
|
||||
CDN_bmux2 g16_dup_1(.sel0 (n_7), .data0 (dpath_b_reg$out[4]), .data1
|
||||
(req_msg[20]), .z (n_485));
|
||||
endmodule
|
||||
|
||||
`ifdef RC_CDN_GENERIC_GATE
|
||||
`else
|
||||
module CDN_flop(clk, d, sena, aclr, apre, srl, srd, q);
|
||||
input clk, d, sena, aclr, apre, srl, srd;
|
||||
output q;
|
||||
wire clk, d, sena, aclr, apre, srl, srd;
|
||||
wire q;
|
||||
reg qi;
|
||||
assign #1 q = qi;
|
||||
always
|
||||
@(posedge clk or posedge apre or posedge aclr)
|
||||
if (aclr)
|
||||
qi <= 0;
|
||||
else if (apre)
|
||||
qi <= 1;
|
||||
else if (srl)
|
||||
qi <= srd;
|
||||
else begin
|
||||
if (sena)
|
||||
qi <= d;
|
||||
end
|
||||
initial
|
||||
qi <= 1'b0;
|
||||
endmodule
|
||||
`endif
|
||||
`ifdef RC_CDN_GENERIC_GATE
|
||||
`else
|
||||
`ifdef ONE_HOT_MUX // captures one-hot property of select inputs
|
||||
module CDN_mux2(sel0, data0, sel1, data1, z);
|
||||
input sel0, data0, sel1, data1;
|
||||
output z;
|
||||
wire sel0, data0, sel1, data1;
|
||||
reg z;
|
||||
always
|
||||
@(sel0 or sel1 or data0 or data1)
|
||||
case ({sel0, sel1})
|
||||
2'b10: z = data0;
|
||||
2'b01: z = data1;
|
||||
default: z = 1'bX;
|
||||
endcase
|
||||
endmodule
|
||||
`else
|
||||
module CDN_mux2(sel0, data0, sel1, data1, z);
|
||||
input sel0, data0, sel1, data1;
|
||||
output z;
|
||||
wire sel0, data0, sel1, data1;
|
||||
wire z;
|
||||
wire w_0, w_1;
|
||||
and a_0 (w_0, sel0, data0);
|
||||
and a_1 (w_1, sel1, data1);
|
||||
or org (z, w_0, w_1);
|
||||
endmodule
|
||||
`endif // ONE_HOT_MUX
|
||||
`endif
|
||||
`ifdef RC_CDN_GENERIC_GATE
|
||||
`else
|
||||
`ifdef ONE_HOT_MUX
|
||||
module CDN_bmux2(sel0, data0, data1, z);
|
||||
input sel0, data0, data1;
|
||||
output z;
|
||||
wire sel0, data0, data1;
|
||||
reg z;
|
||||
always
|
||||
@(sel0 or data0 or data1)
|
||||
case ({sel0})
|
||||
1'b0: z = data0;
|
||||
1'b1: z = data1;
|
||||
endcase
|
||||
endmodule
|
||||
`else
|
||||
module CDN_bmux2(sel0, data0, data1, z);
|
||||
input sel0, data0, data1;
|
||||
output z;
|
||||
wire sel0, data0, data1;
|
||||
wire z;
|
||||
wire inv_sel0, w_0, w_1;
|
||||
not i_0 (inv_sel0, sel0);
|
||||
and a_0 (w_0, inv_sel0, data0);
|
||||
and a_1 (w_1, sel0, data1);
|
||||
or org (z, w_0, w_1);
|
||||
endmodule
|
||||
`endif // ONE_HOT_MUX
|
||||
`endif
|
||||
`ifdef RC_CDN_GENERIC_GATE
|
||||
`else
|
||||
`ifdef ONE_HOT_MUX
|
||||
module CDN_bmux4(sel0, data0, data1, sel1, data2, data3, z);
|
||||
input sel0, data0, data1, sel1, data2, data3;
|
||||
output z;
|
||||
wire sel0, data0, data1, sel1, data2, data3;
|
||||
reg z;
|
||||
always
|
||||
@(sel0 or sel1 or data0 or data1 or data2 or data3)
|
||||
case ({sel0, sel1})
|
||||
2'b00: z = data0;
|
||||
2'b10: z = data1;
|
||||
2'b01: z = data2;
|
||||
2'b11: z = data3;
|
||||
endcase
|
||||
endmodule
|
||||
`else
|
||||
module CDN_bmux4(sel0, data0, data1, sel1, data2, data3, z);
|
||||
input sel0, data0, data1, sel1, data2, data3;
|
||||
output z;
|
||||
wire sel0, data0, data1, sel1, data2, data3;
|
||||
wire z;
|
||||
wire inv_sel0, inv_sel1, w_0, w_1, w_2, w_3;
|
||||
not i_0 (inv_sel0, sel0);
|
||||
not i_1 (inv_sel1, sel1);
|
||||
and a_0 (w_0, inv_sel1, inv_sel0, data0);
|
||||
and a_1 (w_1, inv_sel1, sel0, data1);
|
||||
and a_2 (w_2, sel1, inv_sel0, data2);
|
||||
and a_3 (w_3, sel1, sel0, data3);
|
||||
or org (z, w_0, w_1, w_2, w_3);
|
||||
endmodule
|
||||
`endif // ONE_HOT_MUX
|
||||
`endif
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
# ####################################################################
|
||||
|
||||
# Created by Genus(TM) Synthesis Solution 19.12-s121_1 on Mon Aug 10 11:16:47 CST 2020
|
||||
|
||||
# ####################################################################
|
||||
|
||||
set sdc_version 2.0
|
||||
|
||||
set_units -capacitance 1000fF
|
||||
set_units -time 1000ps
|
||||
|
||||
# Set the current design
|
||||
current_design gcd
|
||||
|
||||
create_clock -name "clk" -period 0.1 -waveform {0.0 0.05} [get_ports clk]
|
||||
set_clock_transition 0.4 [get_clocks clk]
|
||||
set_clock_gating_check -setup 0.0
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports resp_rdy]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports reset]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports req_val]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[0]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[1]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[2]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[3]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[4]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[5]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[6]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[7]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[8]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[9]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[10]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[11]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[12]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[13]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[14]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[15]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[16]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[17]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[18]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[19]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[20]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[21]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[22]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[23]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[24]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[25]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[26]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[27]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[28]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[29]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[30]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {req_msg[31]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports clk]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports resp_val]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[0]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[1]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[2]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[3]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[4]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[5]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[6]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[7]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[8]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[9]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[10]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[11]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[12]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[13]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[14]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {resp_msg[15]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports req_rdy]
|
||||
set_wire_load_mode "enclosed"
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
Instance: /gcd
|
||||
Power Unit: W
|
||||
PDB Frames: /stim#0/frame#0
|
||||
-------------------------------------------------------------------------
|
||||
Category Leakage Internal Switching Total Row%
|
||||
-------------------------------------------------------------------------
|
||||
memory 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
register 1.86923e-06 1.98160e-03 0.00000e+00 1.98347e-03 53.24%
|
||||
latch 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
logic 2.34543e-06 1.73943e-03 0.00000e+00 1.74178e-03 46.76%
|
||||
bbox 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
clock 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
pad 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
pm 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
-------------------------------------------------------------------------
|
||||
Subtotal 4.21466e-06 3.72103e-03 0.00000e+00 3.72524e-03 100.00%
|
||||
Percentage 0.11% 99.89% 0.00% 100.00% 100.00%
|
||||
-------------------------------------------------------------------------
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
============================================================
|
||||
Generated by: Genus(TM) Synthesis Solution 19.12-s121_1
|
||||
Generated on: Aug 10 2020 11:16:47 am
|
||||
Module: gcd
|
||||
Technology library: gscl45nm
|
||||
Operating conditions: typical (balanced_tree)
|
||||
Wireload mode: enclosed
|
||||
Area mode: timing library
|
||||
============================================================
|
||||
|
||||
Pin Type Fanout Load Slew Delay Arrival
|
||||
(fF) (ps) (ps) (ps)
|
||||
-------------------------------------------------------------------------
|
||||
(clock clk) launch 0 R
|
||||
dpath_b_reg
|
||||
out_reg[1]/clk 400 0 R
|
||||
out_reg[1]/q (u) unmapped_d_flop 6 25.2 0 +191 191 F
|
||||
dpath_b_reg/out[1]
|
||||
dpath_sub_sub_752_15/B[1]
|
||||
g16/in_0 +0 191
|
||||
g16/z (u) unmapped_not 2 9.0 0 +42 233 R
|
||||
g23/in_1 +0 233
|
||||
g23/z (u) unmapped_nor2 1 4.2 0 +41 274 F
|
||||
g53/in_0 +0 274
|
||||
g53/z (u) unmapped_not 2 9.0 0 +42 316 R
|
||||
g54/in_1 +0 316
|
||||
g54/z (u) unmapped_nand2 1 4.2 0 +41 356 F
|
||||
g55/in_1 +0 356
|
||||
g55/z (u) unmapped_nand2 3 13.5 0 +58 414 R
|
||||
g87/in_1 +0 414
|
||||
g87/z (u) unmapped_nand2 1 4.2 0 +41 454 F
|
||||
g88/in_1 +0 454
|
||||
g88/z (u) unmapped_nand2 5 22.5 0 +65 519 R
|
||||
g128/in_0 +0 519
|
||||
g128/z (u) unmapped_nand2 1 4.2 0 +41 560 F
|
||||
g129/in_1 +0 560
|
||||
g129/z (u) unmapped_nand2 8 36.0 0 +76 636 R
|
||||
g162/in_1 +0 636
|
||||
g162/z (u) unmapped_nand2 1 4.2 0 +41 677 F
|
||||
g163/in_1 +0 677
|
||||
g163/z (u) unmapped_nand2 1 4.5 0 +41 718 R
|
||||
g203/in_0 +0 718
|
||||
g203/z (u) unmapped_xnor2 2 4.5 0 +76 794 R
|
||||
dpath_sub_sub_752_15/Z[15]
|
||||
g48/data0 +0 794
|
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g48/z (u) unmapped_bmux3 1 4.5 0 +76 870 R
|
||||
g49/data0 +0 870
|
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g49/z (u) unmapped_bmux3 1 4.5 0 +76 947 R
|
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dpath_a_reg/in_[15]
|
||||
g49_g1/data1 +0 947
|
||||
g49_g1/z (u) unmapped_mux4 1 4.5 0 +71 1018 R
|
||||
out_reg[15]/d <<< unmapped_d_flop +0 1018
|
||||
out_reg[15]/clk setup 400 +56 1074 R
|
||||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
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(clock clk) capture 100 R
|
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-------------------------------------------------------------------------
|
||||
Timing slack : -974ps (TIMING VIOLATION)
|
||||
Start-point : dpath_b_reg/out_reg[1]/clk
|
||||
End-point : dpath_a_reg/out_reg[15]/d
|
||||
|
||||
(u) : Net has unmapped pin(s).
|
||||
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
all:
|
||||
genus -legacy_ui -batch -files ../scripts/gcd_to_synth.tcl
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
set hdl_files {gcd.v}
|
||||
set DESIGN gcd
|
||||
set clkpin clk
|
||||
set delay 100
|
||||
set_attribute hdl_search_path /home/jxzhang/projects/cocoon/design/gcd/hdl
|
||||
set_attribute lib_search_path /home/jxzhang/projects/cocoon/design/lib
|
||||
set_attribute information_level 6
|
||||
set_attribute library gscl45nm.lib
|
||||
read_hdl ${hdl_files}
|
||||
elaborate $DESIGN
|
||||
set clock [define_clock -period ${delay} -name ${clkpin} [clock_ports]]
|
||||
external_delay -input 0 -clock clk [find / -port ports_in/*]
|
||||
external_delay -output 0 -clock clk [find / -port ports_out/*]
|
||||
dc::set_clock_transition .4 clk
|
||||
check_design -unresolved
|
||||
report timing -lint
|
||||
synthesize -effort -is_incremental
|
||||
report timing > /home/jxzhang/projects/cocoon/design/gcd/gscl45nm/reports/timing_synth.rpt
|
||||
report gates > /home/jxzhang/projects/cocoon/design/gcd/gscl45nm/reports/gates_synth.rpt
|
||||
report power > /home/jxzhang/projects/cocoon/design/gcd/gscl45nm/reports/gates_synth.rpt
|
||||
write_hdl -mapped > /home/jxzhang/projects/cocoon/design/gcd/gscl45nm/objects/gcd.vh
|
||||
write_sdc > /home/jxzhang/projects/cocoon/design/gcd/gscl45nm/objects/gcd_synth.sdc
|
||||
14
engine.py
14
engine.py
|
|
@ -1,4 +1,5 @@
|
|||
import subprocess
|
||||
import os
|
||||
import util
|
||||
import ops.cds.syn as syn1
|
||||
import ops.openroad.syn as syn2
|
||||
|
|
@ -8,15 +9,20 @@ def run(design, flow):
|
|||
for x in flow.ops:
|
||||
if x[0] == "GenusSynth":
|
||||
run_path = util.getRunPath(design, "Cadence")
|
||||
make_file = open("Makefile", "w")
|
||||
script_path = "../scripts/"
|
||||
print(run_path)
|
||||
make_file = open(run_path + "/" + "Makefile", "w")
|
||||
tmpop = eval("syn1." + "GenusSynth" + "(design)")
|
||||
tmpop.config(design, design_name + "_" + x[1])
|
||||
make_file.write("all:\n")
|
||||
make_file.write("\tgenus -legacy_ui -batch -files " + design_name + "_" + x[1] + ".tcl\n")
|
||||
make_file.write("\tgenus -legacy_ui -batch -files " + script_path + design_name + "_" + x[1] + ".tcl\n")
|
||||
#if x[0] == "OpenROADSynth":
|
||||
|
||||
#cmd = 'make'
|
||||
#subprocess.Popen(cmd)
|
||||
run_path = util.getRunPath(design, "Cadence")
|
||||
os.chdir(run_path)
|
||||
print(os.getcwd())
|
||||
cmd = 'make'
|
||||
subprocess.Popen(cmd)
|
||||
|
||||
return 0
|
||||
|
||||
|
|
|
|||
|
|
@ -28,12 +28,12 @@ class GenusSynth():
|
|||
|
||||
def getObjHDL(self):
|
||||
obj_path = util.getObjPath(self.design, "Cadence")
|
||||
obj_hdl = obj_pat + "/" + self.design.top_name + ".vh"
|
||||
obj_hdl = obj_path + "/" + self.design.top_name + ".vh"
|
||||
return obj_hdl
|
||||
|
||||
def getObjSDC(self):
|
||||
obj_path = util.getObjPath(self.design, "Cadence")
|
||||
obj_sdc = obj_pat + "/" + self.design.top_name + "_synth.sdc"
|
||||
obj_sdc = obj_path + "/" + self.design.top_name + "_synth.sdc"
|
||||
return obj_sdc
|
||||
|
||||
def getRptGates(self):
|
||||
|
|
@ -46,7 +46,7 @@ class GenusSynth():
|
|||
rpt_timing = rpt_path + "/" + "timing_synth.rpt"
|
||||
return rpt_timing
|
||||
|
||||
def getRptGates(self):
|
||||
def getRptPower(self):
|
||||
rpt_path = util.getRptPath(self.design, "Cadence")
|
||||
rpt_power = rpt_path + "/" + "gates_synth.rpt"
|
||||
return rpt_power
|
||||
|
|
@ -75,7 +75,7 @@ class GenusSynth():
|
|||
tcl.write('set delay %d\n'%(self.design.delay))
|
||||
#tcl.write('set_attribute hdl_search_path %s\n'%(self.design.hdl_path))
|
||||
#tcl.write('set_attribute lib_search_path %s\n'%(self.design.lib_path))
|
||||
tcl.write('set_attribute hdl_search_path %s\n'%(shdl_path))
|
||||
tcl.write('set_attribute hdl_search_path %s\n'%(hdl_path))
|
||||
tcl.write('set_attribute lib_search_path %s\n'%(lib_path))
|
||||
tcl.write('set_attribute information_level 6 \n')
|
||||
tcl.write('set_attribute library %s\n'%(lib_file))
|
||||
|
|
|
|||
14
util.py
14
util.py
|
|
@ -9,49 +9,49 @@ def getLef(design):
|
|||
|
||||
def getHDLPath(design, baseflow):
|
||||
if baseflow == "Cadence":
|
||||
hdl_path = "./design/" + design.top_name + "/hdl"
|
||||
hdl_path = "/home/jxzhang/projects/cocoon/design/" + design.top_name + "/hdl"
|
||||
elif baseflow == "Openroad":
|
||||
hdl_path = "/OpenROAD-flow/flow/designs/design/" + design.top_name + "/hdl"
|
||||
return hdl_path
|
||||
|
||||
def getLibPath(design, baseflow):
|
||||
if baseflow == "Cadence":
|
||||
lib_path = "./design/lib"
|
||||
lib_path = "/home/jxzhang/projects/cocoon/design/lib"
|
||||
elif baseflow == "Openroad":
|
||||
lib_path = "/OpenROAD-flow/flow/platforms/" + design.lib_name
|
||||
return lib_path
|
||||
|
||||
def getLefPath(design, baseflow):
|
||||
if baseflow == "Cadence":
|
||||
lef_path = "./design/lib"
|
||||
lef_path = "/home/jxzhang/projects/cocoon/design/lib"
|
||||
elif baseflow == "Openroad":
|
||||
lef_path = ""
|
||||
return lef_path
|
||||
|
||||
def getRptPath(design, baseflow):
|
||||
if baseflow == "Cadence":
|
||||
rpt_path = "./design/" + design.top_name + "/" + design.lib_name + "/reports"
|
||||
rpt_path = "/home/jxzhang/projects/cocoon/design/" + design.top_name + "/" + design.lib_name + "/reports"
|
||||
elif baseflow == "Openroad":
|
||||
rpt_path = "/OpenROAD-flow/flow" + design.top_name + "/" + design.lib_name + "/reports"
|
||||
return rpt_path
|
||||
|
||||
def getObjPath(design, baseflow):
|
||||
if baseflow == "Cadence":
|
||||
obj_path = "./design/" + design.top_name + "/" + design.lib_name + "/objects"
|
||||
obj_path = "/home/jxzhang/projects/cocoon/design/" + design.top_name + "/" + design.lib_name + "/objects"
|
||||
elif baseflow == "Openroad":
|
||||
obj_path = "/OpenROAD-flow/flow" + design.top_name + "/" + design.lib_name + "/objects"
|
||||
return obj_path
|
||||
|
||||
def getScriptPath(design, baseflow):
|
||||
if baseflow == "Cadence":
|
||||
script_path = "./design/" + design.top_name + "/" + design.lib_name + "/scripts"
|
||||
script_path = "/home/jxzhang/projects/cocoon/design/" + design.top_name + "/" + design.lib_name + "/scripts"
|
||||
elif baseflow == "Openroad":
|
||||
script_path = "/OpenROAD-flow/flow" + design.top_name + "/" + design.lib_name + "/scripts"
|
||||
return script_path
|
||||
|
||||
def getRunPath(design, baseflow):
|
||||
if baseflow == "Cadence":
|
||||
run_path = "./design/" + design.top_name + "/" + design.lib_name + "/run"
|
||||
run_path = "/home/jxzhang/projects/cocoon/design/" + design.top_name + "/" + design.lib_name + "/run"
|
||||
elif baseflow == "Openroad":
|
||||
run_path = "/OpenROAD-flow/flow" + design.top_name + "/" + design.lib_name + "/run"
|
||||
return run_path
|
||||
Loading…
Reference in New Issue