add initial version
This commit is contained in:
zjxzjxzjx
commit
2995a1be9c
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class Design(object):
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def __init__(self, top_name):
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self.top_name = top_name
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self.rtl_file = "{TopModuleWrapper.v}"
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self.hdl_path = "./design/cgra/hdl"
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self.lib_path = "./design/lib"
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self.mmmc_file = "{./flow.view}"
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self.lef_file = self.lib_path + "/gscl45nm.lef"
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self.lib_file = "gscl45nm.lib"
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self.clk_name = "clk"
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self.delay = 10000
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self.rpt_path = "./design/cgra/report"
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self.obj_path = "./design/cgra/object"
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self.script_path = "./design/cgra/scripts"
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set hdl_files {TopModuleWrapper.v}
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set DESIGN TopModuleWrapper
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set clkpin clk
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set delay 10000
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set_attribute hdl_search_path ./design/cgra/hdl
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set_attribute lib_search_path ./design/lib
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set_attribute information_level 6
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set_attribute library gscl45nm.lib
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read_hdl ${hdl_files}
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elaborate $DESIGN
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set clock [define_clock -period ${delay} -name ${clkpin} [clock_ports]]
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external_delay -input 0 -clock clk [find / -port ports_in/*]
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external_delay -output 0 -clock clk [find / -port ports_out/*]
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dc::set_clock_transition .4 clk
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check_design -unresolved
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report timing -lint
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synthesize -effort -is_incremental
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report timing > ./design/cgra/report/timing_synth.rpt
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report gates > ./design/cgra/report/gates_synth.rpt
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report power > ./design/cgra/report/power_synth.rpt
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write_hdl -mapped > ./design/cgra/object/TopModuleWrapper.vh
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write_sdc > ./design/cgra/object/TopModuleWrapper_synth.sdc
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,26 @@
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module behav_counter(d, clk, clear, load, up_down, qd);
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input [7:0] d;
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input clk;
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input clear;
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input load;
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input up_down;
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output [7:0] qd;
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reg [7:0] cnt;
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always @ (posedge clk)
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begin
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if (!clear)
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cnt <= 8'h00;
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else if (load)
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cnt <= d;
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else if (up_down)
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cnt <= cnt + 1;
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else
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cnt <= cnt - 1;
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end
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assign qd = cnt;
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endmodule
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,370 @@
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# ####################################################################
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# Created by Genus(TM) Synthesis Solution 19.12-s121_1 on Sat Aug 01 20:42:27 CST 2020
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# ####################################################################
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set sdc_version 2.0
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set_units -capacitance 1000fF
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set_units -time 1000ps
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# Set the current design
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current_design TopModuleWrapper
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create_clock -name "clk" -period 10.0 -waveform {0.0 5.0} [get_ports clock]
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set_clock_transition 0.4 [get_clocks clk]
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set_clock_gating_check -setup 0.0
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[0]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[1]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[2]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[3]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[4]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[5]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[6]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[7]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[8]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[9]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[10]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[11]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[12]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[13]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[14]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[15]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[16]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[17]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[18]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[19]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[20]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[21]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[22]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[23]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[24]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[25]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[26]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[27]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[28]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[29]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[30]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_0[31]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[0]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[1]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[2]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[3]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[4]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[5]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[6]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[7]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[8]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[9]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[10]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[11]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[12]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[13]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[14]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[15]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[16]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[17]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[18]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[19]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[20]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[21]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[22]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[23]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[24]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[25]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[26]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[27]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[28]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[29]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[30]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_1[31]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[0]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[1]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[2]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[3]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[4]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[5]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[6]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[7]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[8]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[9]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[10]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[11]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[12]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[13]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[14]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[15]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[16]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[17]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[18]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[19]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[20]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[21]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[22]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[23]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[24]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[25]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[26]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[27]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[28]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[29]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[30]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_2[31]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[0]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[1]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[2]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[3]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[4]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[5]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[6]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[7]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[8]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[9]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[10]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[11]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[12]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[13]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[14]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[15]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[16]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[17]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[18]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[19]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[20]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[21]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[22]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[23]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[24]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[25]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[26]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[27]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[28]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[29]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[30]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_inputs_3[31]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_II[0]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_II[1]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_II[2]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports io_en]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_LSUnitID[0]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_LSUnitID[1]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports io_deqEnLSU]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports io_enqEnLSU]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports io_startLSU]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_lenLSU[0]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_lenLSU[1]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_lenLSU[2]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_lenLSU[3]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_lenLSU[4]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_lenLSU[5]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_lenLSU[6]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_lenLSU[7]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_baseLSU[0]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_baseLSU[1]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_baseLSU[2]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_baseLSU[3]}]
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set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_baseLSU[4]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_baseLSU[5]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_baseLSU[6]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_baseLSU[7]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports io_streamOutLSU_ready]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[0]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[1]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[2]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[3]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[4]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[5]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[6]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[7]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[8]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[9]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[10]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[11]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[12]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[13]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[14]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[15]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[16]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[17]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[18]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[19]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[20]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[21]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[22]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[23]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[24]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[25]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[26]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[27]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[28]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[29]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[30]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamInLSU_bits[31]}]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports io_streamInLSU_valid]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports reset]
|
||||
set_input_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports clock]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[0]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[1]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[2]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[3]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[4]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[5]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[6]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[7]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[8]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[9]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[10]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[11]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[12]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[13]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[14]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[15]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[16]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[17]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[18]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[19]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[20]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[21]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[22]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[23]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[24]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[25]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[26]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[27]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[28]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[29]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[30]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_0[31]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[0]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[1]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[2]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[3]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[4]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[5]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[6]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[7]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[8]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[9]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[10]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[11]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[12]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[13]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[14]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[15]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[16]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[17]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[18]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[19]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[20]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[21]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[22]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[23]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[24]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[25]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[26]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[27]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[28]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[29]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[30]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_1[31]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[0]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[1]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[2]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[3]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[4]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[5]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[6]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[7]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[8]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[9]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[10]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[11]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[12]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[13]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[14]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[15]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[16]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[17]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[18]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[19]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[20]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[21]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[22]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[23]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[24]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[25]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[26]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[27]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[28]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[29]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[30]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_2[31]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[0]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[1]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[2]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[3]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[4]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[5]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[6]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[7]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[8]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[9]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[10]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[11]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[12]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[13]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[14]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[15]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[16]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[17]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[18]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[19]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[20]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[21]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[22]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[23]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[24]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[25]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[26]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[27]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[28]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[29]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[30]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_outs_3[31]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports io_idleLSU]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[0]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[1]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[2]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[3]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[4]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[5]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[6]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[7]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[8]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[9]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[10]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[11]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[12]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[13]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[14]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[15]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[16]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[17]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[18]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[19]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[20]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[21]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[22]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[23]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[24]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[25]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[26]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[27]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[28]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[29]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[30]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports {io_streamOutLSU_bits[31]}]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports io_streamOutLSU_valid]
|
||||
set_output_delay -clock [get_clocks clk] -add_delay 0.0 [get_ports io_streamInLSU_ready]
|
||||
set_wire_load_mode "enclosed"
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
============================================================
|
||||
Generated by: Genus(TM) Synthesis Solution 19.12-s121_1
|
||||
Generated on: Aug 01 2020 08:42:19 pm
|
||||
Module: TopModuleWrapper
|
||||
Technology library: gscl45nm
|
||||
Operating conditions: typical (balanced_tree)
|
||||
Wireload mode: enclosed
|
||||
Area mode: timing library
|
||||
============================================================
|
||||
|
||||
|
||||
Type Instances Area Area %
|
||||
--------------------------------------
|
||||
sequential 37256 0.000 0.0
|
||||
inverter 6133 0.000 0.0
|
||||
logic 38506 0.000 0.0
|
||||
physical_cells 0 0.000 0.0
|
||||
--------------------------------------
|
||||
total 81895 0.000 0.0
|
||||
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
Instance: /TopModuleWrapper
|
||||
Power Unit: W
|
||||
PDB Frames: /stim#0/frame#0
|
||||
-------------------------------------------------------------------------
|
||||
Category Leakage Internal Switching Total Row%
|
||||
-------------------------------------------------------------------------
|
||||
memory 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
register 2.04824e-03 2.28401e-02 0.00000e+00 2.48883e-02 84.90%
|
||||
latch 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
logic 5.43527e-04 3.88212e-03 0.00000e+00 4.42565e-03 15.10%
|
||||
bbox 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
clock 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
pad 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
pm 0.00000e+00 0.00000e+00 0.00000e+00 0.00000e+00 0.00%
|
||||
-------------------------------------------------------------------------
|
||||
Subtotal 2.59177e-03 2.67222e-02 0.00000e+00 2.93140e-02 100.00%
|
||||
Percentage 8.84% 91.16% 0.00% 100.00% 100.00%
|
||||
-------------------------------------------------------------------------
|
||||
|
|
@ -0,0 +1,529 @@
|
|||
============================================================
|
||||
Generated by: Genus(TM) Synthesis Solution 19.12-s121_1
|
||||
Generated on: Aug 01 2020 08:42:16 pm
|
||||
Module: TopModuleWrapper
|
||||
Technology library: gscl45nm
|
||||
Operating conditions: typical (balanced_tree)
|
||||
Wireload mode: enclosed
|
||||
Area mode: timing library
|
||||
============================================================
|
||||
|
||||
Pin Type Fanout Load Slew Delay Arrival
|
||||
(fF) (ps) (ps) (ps)
|
||||
------------------------------------------------------------------------------------------------
|
||||
(clock clk) launch 0 R
|
||||
topModule
|
||||
configController_cycleReg_reg[0]/clk 400 0 R
|
||||
configController_cycleReg_reg[0]/q (u) unmapped_d_flop 11 46.2 0 +204 204 F
|
||||
g59978/in_0 +0 204
|
||||
g59978/z (u) unmapped_not 6 27.0 0 +60 264 R
|
||||
g60340/in_0 +0 264
|
||||
g60340/z (u) unmapped_nand3 2 8.4 0 +62 326 F
|
||||
g737/in_0 +0 326
|
||||
g737/z (u) unmapped_nor2 2 9.0 0 +51 376 R
|
||||
topDispatch_mux_2797_23_g52184/sel8 +0 376
|
||||
topDispatch_mux_2797_23_g52184/z (u) unmapped_mux18 468 2106.0 0 +245 621 R
|
||||
RegisterFiles/io_configuration[27]
|
||||
g6723/in_0 +0 621
|
||||
g6723/z (u) unmapped_not 3 12.6 0 +49 670 F
|
||||
g6747/in_1 +0 670
|
||||
g6747/z (u) unmapped_nor3 1 4.5 0 +52 722 R
|
||||
g6748/in_0 +0 722
|
||||
g6748/z (u) unmapped_not 2 8.4 0 +42 764 F
|
||||
g6809/in_0 +0 764
|
||||
g6809/z (u) unmapped_nor2 32 144.0 0 +104 868 R
|
||||
mux_912_22_g62/sel3 +0 868
|
||||
mux_912_22_g62/z (u) unmapped_mux18 7 31.5 0 +160 1029 R
|
||||
RegisterFiles/io_outs_5[1]
|
||||
g73311/in_0 +0 1029
|
||||
g73311/z (u) unmapped_and2 1 4.5 0 +41 1069 R
|
||||
g73313/in_0 +0 1069
|
||||
g73313/z (u) unmapped_or2 1 4.5 0 +41 1110 R
|
||||
g73314/in_1 +0 1110
|
||||
g73314/z (u) unmapped_or2 2 9.0 0 +51 1161 R
|
||||
Alu_3_syncScheduleController_regNextN/io_input[1]
|
||||
mux_30_19_g317/data0 +0 1161
|
||||
mux_30_19_g317/z (u) unmapped_mux8 111 499.5 0 +184 1344 R
|
||||
Alu_3_syncScheduleController_regNextN/io_out[1]
|
||||
Alu_3_div_202_57/B[1]
|
||||
g765/in_0 +0 1344
|
||||
g765/z (u) unmapped_nor2 2 8.4 0 +51 1395 F
|
||||
g234/in_0 +0 1395
|
||||
g234/z (u) unmapped_not 2 9.0 0 +42 1437 R
|
||||
g69/in_1 +0 1437
|
||||
g69/z (u) unmapped_nand2 1 4.2 0 +41 1478 F
|
||||
g70/in_1 +0 1478
|
||||
g70/z (u) unmapped_nand2 3 13.5 0 +58 1535 R
|
||||
g275/in_1 +0 1535
|
||||
g275/z (u) unmapped_nand2 1 4.2 0 +41 1576 F
|
||||
g276/in_1 +0 1576
|
||||
g276/z (u) unmapped_nand2 5 22.5 0 +65 1641 R
|
||||
g339/in_0 +0 1641
|
||||
g339/z (u) unmapped_nand2 1 4.2 0 +41 1681 F
|
||||
g340/in_1 +0 1681
|
||||
g340/z (u) unmapped_nand2 9 40.5 0 +78 1759 R
|
||||
g409/in_1 +0 1759
|
||||
g409/z (u) unmapped_nand2 1 4.2 0 +41 1800 F
|
||||
g410/in_1 +0 1800
|
||||
g410/z (u) unmapped_nand2 17 76.5 0 +91 1891 R
|
||||
g486/in_0 +0 1891
|
||||
g486/z (u) unmapped_nand2 1 4.2 0 +41 1932 F
|
||||
g487/in_1 +0 1932
|
||||
g487/z (u) unmapped_nand2 1 4.5 0 +41 1972 R
|
||||
g570/in_0 +0 1972
|
||||
g570/z (u) unmapped_xnor2 2 8.4 0 +86 2059 F
|
||||
g964/in_1 +0 2059
|
||||
g964/z (u) unmapped_nor2 3 13.5 0 +58 2116 R
|
||||
g989/in_1 +0 2116
|
||||
g989/z (u) unmapped_nand2 5 21.0 0 +65 2181 F
|
||||
g1011/in_1 +0 2181
|
||||
g1011/z (u) unmapped_nor2 6 27.0 0 +69 2250 R
|
||||
g1033/in_1 +0 2250
|
||||
g1033/z (u) unmapped_nand2 1 4.2 0 +41 2290 F
|
||||
g1059/in_0 +0 2290
|
||||
g1059/z (u) unmapped_not 8 36.0 0 +68 2358 R
|
||||
g1060/in_1 +0 2358
|
||||
g1060/z (u) unmapped_nand2 1 4.2 0 +41 2399 F
|
||||
g1114/in_0 +0 2399
|
||||
g1114/z (u) unmapped_not 1 4.5 0 +32 2431 R
|
||||
g1063/in_1 +0 2431
|
||||
g1063/z (u) unmapped_nand2 3 12.6 0 +58 2488 F
|
||||
g4/in_1 +0 2488
|
||||
g4/z (u) unmapped_and2 2 8.4 0 +51 2539 F
|
||||
g1131/sel2 +0 2539
|
||||
g1131/z (u) unmapped_mux8 7 29.4 0 +139 2678 F
|
||||
g1337/in_0 +0 2678
|
||||
g1337/z (u) unmapped_nor2 3 13.5 0 +58 2735 R
|
||||
g1345/in_1 +0 2735
|
||||
g1345/z (u) unmapped_nor2 1 4.2 0 +41 2776 F
|
||||
g1363/in_0 +0 2776
|
||||
g1363/z (u) unmapped_nand2 1 4.5 0 +41 2816 R
|
||||
g1364/in_1 +0 2816
|
||||
g1364/z (u) unmapped_nand2 1 4.2 0 +41 2857 F
|
||||
g1392/in_0 +0 2857
|
||||
g1392/z (u) unmapped_nand2 1 4.5 0 +41 2898 R
|
||||
g1497/in_0 +0 2898
|
||||
g1497/z (u) unmapped_not 1 4.2 0 +32 2930 F
|
||||
g1418/in_1 +0 2930
|
||||
g1418/z (u) unmapped_nand2 1 4.5 0 +41 2971 R
|
||||
g1501/in_0 +0 2971
|
||||
g1501/z (u) unmapped_not 1 4.2 0 +32 3003 F
|
||||
g1456/in_0 +0 3003
|
||||
g1456/z (u) unmapped_nand2 1 4.5 0 +41 3044 R
|
||||
g1509/in_0 +0 3044
|
||||
g1509/z (u) unmapped_not 1 4.2 0 +32 3076 F
|
||||
g1458/in_0 +0 3076
|
||||
g1458/z (u) unmapped_nand2 3 13.5 0 +58 3133 R
|
||||
g15/in_0 +0 3133
|
||||
g15/z (u) unmapped_not 1 4.2 0 +32 3165 F
|
||||
g16/in_0 +0 3165
|
||||
g16/z (u) unmapped_and2 4 16.8 0 +63 3228 F
|
||||
g1729/sel2 +0 3228
|
||||
g1729/z (u) unmapped_mux8 7 29.4 0 +139 3367 F
|
||||
g1954/in_0 +0 3367
|
||||
g1954/z (u) unmapped_nor2 3 13.5 0 +58 3424 R
|
||||
g1966/in_1 +0 3424
|
||||
g1966/z (u) unmapped_nor2 1 4.2 0 +41 3465 F
|
||||
g1987/in_0 +0 3465
|
||||
g1987/z (u) unmapped_nand2 1 4.5 0 +41 3506 R
|
||||
g1988/in_1 +0 3506
|
||||
g1988/z (u) unmapped_nand2 3 12.6 0 +58 3563 F
|
||||
g2022/in_0 +0 3563
|
||||
g2022/z (u) unmapped_nand2 1 4.5 0 +41 3604 R
|
||||
g2023/in_1 +0 3604
|
||||
g2023/z (u) unmapped_nand2 1 4.2 0 +41 3644 F
|
||||
g2049/in_1 +0 3644
|
||||
g2049/z (u) unmapped_nand2 1 4.5 0 +41 3685 R
|
||||
g2133/in_0 +0 3685
|
||||
g2133/z (u) unmapped_not 1 4.2 0 +32 3717 F
|
||||
g2087/in_0 +0 3717
|
||||
g2087/z (u) unmapped_nand2 1 4.5 0 +41 3758 R
|
||||
g2141/in_0 +0 3758
|
||||
g2141/z (u) unmapped_not 1 4.2 0 +32 3790 F
|
||||
g2089/in_0 +0 3790
|
||||
g2089/z (u) unmapped_nand2 3 13.5 0 +58 3848 R
|
||||
g27/in_0 +0 3848
|
||||
g27/z (u) unmapped_not 1 4.2 0 +32 3880 F
|
||||
g28/in_0 +0 3880
|
||||
g28/z (u) unmapped_and2 6 25.2 0 +69 3948 F
|
||||
g2380/sel2 +0 3948
|
||||
g2380/z (u) unmapped_mux8 7 29.4 0 +139 4087 F
|
||||
g2621/in_0 +0 4087
|
||||
g2621/z (u) unmapped_nor2 3 13.5 0 +58 4145 R
|
||||
g2637/in_1 +0 4145
|
||||
g2637/z (u) unmapped_nor2 1 4.2 0 +41 4185 F
|
||||
g2661/in_0 +0 4185
|
||||
g2661/z (u) unmapped_nand2 1 4.5 0 +41 4226 R
|
||||
g2662/in_1 +0 4226
|
||||
g2662/z (u) unmapped_nand2 5 21.0 0 +65 4291 F
|
||||
g2700/in_0 +0 4291
|
||||
g2700/z (u) unmapped_nand2 1 4.5 0 +41 4331 R
|
||||
g2701/in_1 +0 4331
|
||||
g2701/z (u) unmapped_nand2 1 4.2 0 +41 4372 F
|
||||
g2727/in_1 +0 4372
|
||||
g2727/z (u) unmapped_nand2 1 4.5 0 +41 4413 R
|
||||
g2812/in_0 +0 4413
|
||||
g2812/z (u) unmapped_not 1 4.2 0 +32 4445 F
|
||||
g2765/in_0 +0 4445
|
||||
g2765/z (u) unmapped_nand2 1 4.5 0 +41 4486 R
|
||||
g2820/in_0 +0 4486
|
||||
g2820/z (u) unmapped_not 1 4.2 0 +32 4518 F
|
||||
g2767/in_0 +0 4518
|
||||
g2767/z (u) unmapped_nand2 3 13.5 0 +58 4575 R
|
||||
g39/in_0 +0 4575
|
||||
g39/z (u) unmapped_not 1 4.2 0 +32 4607 F
|
||||
g40/in_0 +0 4607
|
||||
g40/z (u) unmapped_and2 8 33.6 0 +76 4684 F
|
||||
g3075/sel2 +0 4684
|
||||
g3075/z (u) unmapped_mux8 7 29.4 0 +139 4822 F
|
||||
g3343/in_0 +0 4822
|
||||
g3343/z (u) unmapped_nor2 3 13.5 0 +58 4880 R
|
||||
g3363/in_1 +0 4880
|
||||
g3363/z (u) unmapped_nor2 1 4.2 0 +41 4920 F
|
||||
g3390/in_0 +0 4920
|
||||
g3390/z (u) unmapped_nand2 1 4.5 0 +41 4961 R
|
||||
g3391/in_1 +0 4961
|
||||
g3391/z (u) unmapped_nand2 5 21.0 0 +65 5026 F
|
||||
g3432/in_0 +0 5026
|
||||
g3432/z (u) unmapped_nand2 1 4.5 0 +41 5066 R
|
||||
g3433/in_1 +0 5066
|
||||
g3433/z (u) unmapped_nand2 3 12.6 0 +58 5124 F
|
||||
g3470/in_1 +0 5124
|
||||
g3470/z (u) unmapped_nand2 1 4.5 0 +41 5165 R
|
||||
g3471/in_1 +0 5165
|
||||
g3471/z (u) unmapped_nand2 1 4.2 0 +41 5205 F
|
||||
g3509/in_0 +0 5205
|
||||
g3509/z (u) unmapped_nand2 1 4.5 0 +41 5246 R
|
||||
g3565/in_0 +0 5246
|
||||
g3565/z (u) unmapped_not 1 4.2 0 +32 5278 F
|
||||
g3511/in_0 +0 5278
|
||||
g3511/z (u) unmapped_nand2 3 13.5 0 +58 5336 R
|
||||
g51/in_0 +0 5336
|
||||
g51/z (u) unmapped_not 1 4.2 0 +32 5368 F
|
||||
g52/in_0 +0 5368
|
||||
g52/z (u) unmapped_and2 10 42.0 0 +80 5448 F
|
||||
g3847/sel2 +0 5448
|
||||
g3847/z (u) unmapped_mux8 7 29.4 0 +139 5586 F
|
||||
g4131/in_0 +0 5586
|
||||
g4131/z (u) unmapped_nor2 3 13.5 0 +58 5644 R
|
||||
g4155/in_1 +0 5644
|
||||
g4155/z (u) unmapped_nor2 1 4.2 0 +41 5684 F
|
||||
g4185/in_0 +0 5684
|
||||
g4185/z (u) unmapped_nand2 1 4.5 0 +41 5725 R
|
||||
g4186/in_1 +0 5725
|
||||
g4186/z (u) unmapped_nand2 5 21.0 0 +65 5790 F
|
||||
g4231/in_0 +0 5790
|
||||
g4231/z (u) unmapped_nand2 1 4.5 0 +41 5831 R
|
||||
g4232/in_1 +0 5831
|
||||
g4232/z (u) unmapped_nand2 5 21.0 0 +65 5895 F
|
||||
g4269/in_1 +0 5895
|
||||
g4269/z (u) unmapped_nand2 1 4.5 0 +41 5936 R
|
||||
g4270/in_1 +0 5936
|
||||
g4270/z (u) unmapped_nand2 1 4.2 0 +41 5977 F
|
||||
g4308/in_0 +0 5977
|
||||
g4308/z (u) unmapped_nand2 1 4.5 0 +41 6017 R
|
||||
g4365/in_0 +0 6017
|
||||
g4365/z (u) unmapped_not 1 4.2 0 +32 6050 F
|
||||
g4310/in_0 +0 6050
|
||||
g4310/z (u) unmapped_nand2 3 13.5 0 +58 6107 R
|
||||
g63/in_0 +0 6107
|
||||
g63/z (u) unmapped_not 1 4.2 0 +32 6139 F
|
||||
g64/in_0 +0 6139
|
||||
g64/z (u) unmapped_and2 12 50.4 0 +83 6222 F
|
||||
g4663/sel2 +0 6222
|
||||
g4663/z (u) unmapped_mux8 7 29.4 0 +139 6361 F
|
||||
g4967/in_0 +0 6361
|
||||
g4967/z (u) unmapped_nor2 3 13.5 0 +58 6418 R
|
||||
g4995/in_1 +0 6418
|
||||
g4995/z (u) unmapped_nor2 1 4.2 0 +41 6459 F
|
||||
g5028/in_0 +0 6459
|
||||
g5028/z (u) unmapped_nand2 1 4.5 0 +41 6500 R
|
||||
g5029/in_1 +0 6500
|
||||
g5029/z (u) unmapped_nand2 5 21.0 0 +65 6565 F
|
||||
g5077/in_0 +0 6565
|
||||
g5077/z (u) unmapped_nand2 1 4.5 0 +41 6605 R
|
||||
g5078/in_1 +0 6605
|
||||
g5078/z (u) unmapped_nand2 7 29.4 0 +73 6678 F
|
||||
g5121/in_1 +0 6678
|
||||
g5121/z (u) unmapped_nand2 1 4.5 0 +41 6719 R
|
||||
g5122/in_1 +0 6719
|
||||
g5122/z (u) unmapped_nand2 1 4.2 0 +41 6759 F
|
||||
g5160/in_0 +0 6759
|
||||
g5160/z (u) unmapped_nand2 1 4.5 0 +41 6800 R
|
||||
g5217/in_0 +0 6800
|
||||
g5217/z (u) unmapped_not 1 4.2 0 +32 6832 F
|
||||
g5162/in_0 +0 6832
|
||||
g5162/z (u) unmapped_nand2 3 13.5 0 +58 6890 R
|
||||
g75/in_0 +0 6890
|
||||
g75/z (u) unmapped_not 1 4.2 0 +32 6922 F
|
||||
g76/in_0 +0 6922
|
||||
g76/z (u) unmapped_and2 14 58.8 0 +87 7008 F
|
||||
g5535/sel2 +0 7008
|
||||
g5535/z (u) unmapped_mux8 7 29.4 0 +139 7147 F
|
||||
g5859/in_0 +0 7147
|
||||
g5859/z (u) unmapped_nor2 3 13.5 0 +58 7205 R
|
||||
g5891/in_1 +0 7205
|
||||
g5891/z (u) unmapped_nor2 1 4.2 0 +41 7245 F
|
||||
g5927/in_0 +0 7245
|
||||
g5927/z (u) unmapped_nand2 1 4.5 0 +41 7286 R
|
||||
g5928/in_1 +0 7286
|
||||
g5928/z (u) unmapped_nand2 5 21.0 0 +65 7351 F
|
||||
g5980/in_0 +0 7351
|
||||
g5980/z (u) unmapped_nand2 1 4.5 0 +41 7391 R
|
||||
g5981/in_1 +0 7391
|
||||
g5981/z (u) unmapped_nand2 9 37.8 0 +78 7469 F
|
||||
g6026/in_1 +0 7469
|
||||
g6026/z (u) unmapped_nand2 1 4.5 0 +41 7510 R
|
||||
g6027/in_1 +0 7510
|
||||
g6027/z (u) unmapped_nand2 1 4.2 0 +41 7551 F
|
||||
g6065/in_0 +0 7551
|
||||
g6065/z (u) unmapped_nand2 1 4.5 0 +41 7592 R
|
||||
g6125/in_0 +0 7592
|
||||
g6125/z (u) unmapped_not 1 4.2 0 +32 7624 F
|
||||
g6067/in_0 +0 7624
|
||||
g6067/z (u) unmapped_nand2 3 13.5 0 +58 7681 R
|
||||
g87/in_0 +0 7681
|
||||
g87/z (u) unmapped_not 1 4.2 0 +32 7713 F
|
||||
g88/in_0 +0 7713
|
||||
g88/z (u) unmapped_and2 16 67.2 0 +90 7803 F
|
||||
g6463/sel2 +0 7803
|
||||
g6463/z (u) unmapped_mux8 7 29.4 0 +139 7942 F
|
||||
g6837/in_0 +0 7942
|
||||
g6837/z (u) unmapped_nor2 3 13.5 0 +58 7999 R
|
||||
g6873/in_1 +0 7999
|
||||
g6873/z (u) unmapped_nor2 1 4.2 0 +41 8040 F
|
||||
g6912/in_0 +0 8040
|
||||
g6912/z (u) unmapped_nand2 1 4.5 0 +41 8081 R
|
||||
g6913/in_1 +0 8081
|
||||
g6913/z (u) unmapped_nand2 5 21.0 0 +65 8145 F
|
||||
g6968/in_0 +0 8145
|
||||
g6968/z (u) unmapped_nand2 1 4.5 0 +41 8186 R
|
||||
g6969/in_1 +0 8186
|
||||
g6969/z (u) unmapped_nand2 9 37.8 0 +78 8264 F
|
||||
g7018/in_1 +0 8264
|
||||
g7018/z (u) unmapped_nand2 1 4.5 0 +41 8305 R
|
||||
g7019/in_1 +0 8305
|
||||
g7019/z (u) unmapped_nand2 3 12.6 0 +58 8362 F
|
||||
g7085/in_0 +0 8362
|
||||
g7085/z (u) unmapped_nand2 1 4.5 0 +41 8403 R
|
||||
g7086/in_1 +0 8403
|
||||
g7086/z (u) unmapped_nand2 1 4.2 0 +41 8444 F
|
||||
g7088/in_0 +0 8444
|
||||
g7088/z (u) unmapped_nand2 3 13.5 0 +58 8501 R
|
||||
g99/in_0 +0 8501
|
||||
g99/z (u) unmapped_not 1 4.2 0 +32 8533 F
|
||||
g100/in_0 +0 8533
|
||||
g100/z (u) unmapped_and2 18 75.6 0 +92 8625 F
|
||||
g7533/sel2 +0 8625
|
||||
g7533/z (u) unmapped_mux8 7 29.4 0 +139 8764 F
|
||||
g7923/in_0 +0 8764
|
||||
g7923/z (u) unmapped_nor2 3 13.5 0 +58 8821 R
|
||||
g7963/in_1 +0 8821
|
||||
g7963/z (u) unmapped_nor2 1 4.2 0 +41 8862 F
|
||||
g8005/in_0 +0 8862
|
||||
g8005/z (u) unmapped_nand2 1 4.5 0 +41 8903 R
|
||||
g8006/in_1 +0 8903
|
||||
g8006/z (u) unmapped_nand2 5 21.0 0 +65 8967 F
|
||||
g8065/in_0 +0 8967
|
||||
g8065/z (u) unmapped_nand2 1 4.5 0 +41 9008 R
|
||||
g8066/in_1 +0 9008
|
||||
g8066/z (u) unmapped_nand2 9 37.8 0 +78 9086 F
|
||||
g8115/in_1 +0 9086
|
||||
g8115/z (u) unmapped_nand2 1 4.5 0 +41 9127 R
|
||||
g8116/in_1 +0 9127
|
||||
g8116/z (u) unmapped_nand2 5 21.0 0 +65 9192 F
|
||||
g8182/in_0 +0 9192
|
||||
g8182/z (u) unmapped_nand2 1 4.5 0 +41 9232 R
|
||||
g8183/in_1 +0 9232
|
||||
g8183/z (u) unmapped_nand2 1 4.2 0 +41 9273 F
|
||||
g8185/in_0 +0 9273
|
||||
g8185/z (u) unmapped_nand2 3 13.5 0 +58 9330 R
|
||||
g111/in_0 +0 9330
|
||||
g111/z (u) unmapped_not 1 4.2 0 +32 9362 F
|
||||
g112/in_0 +0 9362
|
||||
g112/z (u) unmapped_and2 20 84.0 0 +94 9456 F
|
||||
g8647/sel2 +0 9456
|
||||
g8647/z (u) unmapped_mux8 7 29.4 0 +139 9595 F
|
||||
g9057/in_0 +0 9595
|
||||
g9057/z (u) unmapped_nor2 3 13.5 0 +58 9652 R
|
||||
g9101/in_1 +0 9652
|
||||
g9101/z (u) unmapped_nor2 1 4.2 0 +41 9693 F
|
||||
g9146/in_0 +0 9693
|
||||
g9146/z (u) unmapped_nand2 1 4.5 0 +41 9734 R
|
||||
g9147/in_1 +0 9734
|
||||
g9147/z (u) unmapped_nand2 5 21.0 0 +65 9798 F
|
||||
g9209/in_0 +0 9798
|
||||
g9209/z (u) unmapped_nand2 1 4.5 0 +41 9839 R
|
||||
g9210/in_1 +0 9839
|
||||
g9210/z (u) unmapped_nand2 9 37.8 0 +78 9917 F
|
||||
g9265/in_1 +0 9917
|
||||
g9265/z (u) unmapped_nand2 1 4.5 0 +41 9958 R
|
||||
g9266/in_1 +0 9958
|
||||
g9266/z (u) unmapped_nand2 7 29.4 0 +73 10031 F
|
||||
g9332/in_0 +0 10031
|
||||
g9332/z (u) unmapped_nand2 1 4.5 0 +41 10071 R
|
||||
g9333/in_1 +0 10071
|
||||
g9333/z (u) unmapped_nand2 1 4.2 0 +41 10112 F
|
||||
g9335/in_0 +0 10112
|
||||
g9335/z (u) unmapped_nand2 3 13.5 0 +58 10170 R
|
||||
g123/in_0 +0 10170
|
||||
g123/z (u) unmapped_not 1 4.2 0 +32 10202 F
|
||||
g124/in_0 +0 10202
|
||||
g124/z (u) unmapped_and2 22 92.4 0 +96 10297 F
|
||||
g9817/sel2 +0 10297
|
||||
g9817/z (u) unmapped_mux8 7 29.4 0 +139 10436 F
|
||||
g10247/in_0 +0 10436
|
||||
g10247/z (u) unmapped_nor2 3 13.5 0 +58 10493 R
|
||||
g10295/in_1 +0 10493
|
||||
g10295/z (u) unmapped_nor2 1 4.2 0 +41 10534 F
|
||||
g10343/in_0 +0 10534
|
||||
g10343/z (u) unmapped_nand2 1 4.5 0 +41 10575 R
|
||||
g10344/in_1 +0 10575
|
||||
g10344/z (u) unmapped_nand2 5 21.0 0 +65 10640 F
|
||||
g10410/in_0 +0 10640
|
||||
g10410/z (u) unmapped_nand2 1 4.5 0 +41 10680 R
|
||||
g10411/in_1 +0 10680
|
||||
g10411/z (u) unmapped_nand2 9 37.8 0 +78 10758 F
|
||||
g10468/in_1 +0 10758
|
||||
g10468/z (u) unmapped_nand2 1 4.5 0 +41 10799 R
|
||||
g10469/in_1 +0 10799
|
||||
g10469/z (u) unmapped_nand2 9 37.8 0 +78 10877 F
|
||||
g10535/in_0 +0 10877
|
||||
g10535/z (u) unmapped_nand2 1 4.5 0 +41 10918 R
|
||||
g10536/in_1 +0 10918
|
||||
g10536/z (u) unmapped_nand2 1 4.2 0 +41 10958 F
|
||||
g10538/in_0 +0 10958
|
||||
g10538/z (u) unmapped_nand2 3 13.5 0 +58 11016 R
|
||||
g135/in_0 +0 11016
|
||||
g135/z (u) unmapped_not 1 4.2 0 +32 11048 F
|
||||
g136/in_0 +0 11048
|
||||
g136/z (u) unmapped_and2 24 100.8 0 +97 11145 F
|
||||
g11043/sel2 +0 11145
|
||||
g11043/z (u) unmapped_mux8 7 29.4 0 +139 11284 F
|
||||
g11497/in_0 +0 11284
|
||||
g11497/z (u) unmapped_nor2 3 13.5 0 +58 11342 R
|
||||
g11549/in_1 +0 11342
|
||||
g11549/z (u) unmapped_nor2 1 4.2 0 +41 11382 F
|
||||
g11600/in_0 +0 11382
|
||||
g11600/z (u) unmapped_nand2 1 4.5 0 +41 11423 R
|
||||
g11601/in_1 +0 11423
|
||||
g11601/z (u) unmapped_nand2 5 21.0 0 +65 11488 F
|
||||
g11670/in_0 +0 11488
|
||||
g11670/z (u) unmapped_nand2 1 4.5 0 +41 11528 R
|
||||
g11671/in_1 +0 11528
|
||||
g11671/z (u) unmapped_nand2 9 37.8 0 +78 11606 F
|
||||
g11732/in_1 +0 11606
|
||||
g11732/z (u) unmapped_nand2 1 4.5 0 +41 11647 R
|
||||
g11733/in_1 +0 11647
|
||||
g11733/z (u) unmapped_nand2 11 46.2 0 +82 11729 F
|
||||
g11809/in_0 +0 11729
|
||||
g11809/z (u) unmapped_nand2 1 4.5 0 +41 11769 R
|
||||
g11810/in_1 +0 11769
|
||||
g11810/z (u) unmapped_nand2 1 4.2 0 +41 11810 F
|
||||
g11812/in_0 +0 11810
|
||||
g11812/z (u) unmapped_nand2 3 13.5 0 +58 11868 R
|
||||
g147/in_0 +0 11868
|
||||
g147/z (u) unmapped_not 1 4.2 0 +32 11900 F
|
||||
g148/in_0 +0 11900
|
||||
g148/z (u) unmapped_and2 26 109.2 0 +99 11999 F
|
||||
g12337/sel2 +0 11999
|
||||
g12337/z (u) unmapped_mux8 7 29.4 0 +139 12138 F
|
||||
g12810/in_0 +0 12138
|
||||
g12810/z (u) unmapped_nor2 3 13.5 0 +58 12195 R
|
||||
g12866/in_1 +0 12195
|
||||
g12866/z (u) unmapped_nor2 1 4.2 0 +41 12236 F
|
||||
g12920/in_0 +0 12236
|
||||
g12920/z (u) unmapped_nand2 1 4.5 0 +41 12276 R
|
||||
g12921/in_1 +0 12276
|
||||
g12921/z (u) unmapped_nand2 5 21.0 0 +65 12341 F
|
||||
g12994/in_0 +0 12341
|
||||
g12994/z (u) unmapped_nand2 1 4.5 0 +41 12382 R
|
||||
g12995/in_1 +0 12382
|
||||
g12995/z (u) unmapped_nand2 9 37.8 0 +78 12460 F
|
||||
g13056/in_1 +0 12460
|
||||
g13056/z (u) unmapped_nand2 1 4.5 0 +41 12500 R
|
||||
g13057/in_1 +0 12500
|
||||
g13057/z (u) unmapped_nand2 13 54.6 0 +85 12585 F
|
||||
g13135/in_0 +0 12585
|
||||
g13135/z (u) unmapped_nand2 1 4.5 0 +41 12626 R
|
||||
g13136/in_1 +0 12626
|
||||
g13136/z (u) unmapped_nand2 1 4.2 0 +41 12667 F
|
||||
g13138/in_0 +0 12667
|
||||
g13138/z (u) unmapped_nand2 3 13.5 0 +58 12724 R
|
||||
g159/in_0 +0 12724
|
||||
g159/z (u) unmapped_not 1 4.2 0 +32 12756 F
|
||||
g160/in_0 +0 12756
|
||||
g160/z (u) unmapped_and2 28 117.6 0 +101 12857 F
|
||||
g13684/sel2 +0 12857
|
||||
g13684/z (u) unmapped_mux8 7 29.4 0 +139 12996 F
|
||||
g14185/in_0 +0 12996
|
||||
g14185/z (u) unmapped_nor2 3 13.5 0 +58 13054 R
|
||||
g14245/in_1 +0 13054
|
||||
g14245/z (u) unmapped_nor2 1 4.2 0 +41 13094 F
|
||||
g14302/in_0 +0 13094
|
||||
g14302/z (u) unmapped_nand2 1 4.5 0 +41 13135 R
|
||||
g14303/in_1 +0 13135
|
||||
g14303/z (u) unmapped_nand2 5 21.0 0 +65 13200 F
|
||||
g14379/in_0 +0 13200
|
||||
g14379/z (u) unmapped_nand2 1 4.5 0 +41 13240 R
|
||||
g14380/in_1 +0 13240
|
||||
g14380/z (u) unmapped_nand2 9 37.8 0 +78 13318 F
|
||||
g14447/in_1 +0 13318
|
||||
g14447/z (u) unmapped_nand2 1 4.5 0 +41 13359 R
|
||||
g14448/in_1 +0 13359
|
||||
g14448/z (u) unmapped_nand2 15 63.0 0 +88 13447 F
|
||||
g14530/in_0 +0 13447
|
||||
g14530/z (u) unmapped_nand2 1 4.5 0 +41 13488 R
|
||||
g14531/in_1 +0 13488
|
||||
g14531/z (u) unmapped_nand2 1 4.2 0 +41 13529 F
|
||||
g14533/in_0 +0 13529
|
||||
g14533/z (u) unmapped_nand2 3 13.5 0 +58 13586 R
|
||||
g171/in_0 +0 13586
|
||||
g171/z (u) unmapped_not 1 4.2 0 +32 13618 F
|
||||
g172/in_0 +0 13618
|
||||
g172/z (u) unmapped_and2 30 126.0 0 +103 13721 F
|
||||
g15107/sel2 +0 13721
|
||||
g15107/z (u) unmapped_mux8 6 25.2 0 +135 13856 F
|
||||
g15640/in_0 +0 13856
|
||||
g15640/z (u) unmapped_nor2 2 9.0 0 +51 13906 R
|
||||
g15704/in_1 +0 13906
|
||||
g15704/z (u) unmapped_nor2 2 8.4 0 +51 13957 F
|
||||
g15767/in_1 +0 13957
|
||||
g15767/z (u) unmapped_nand2 1 4.5 0 +41 13998 R
|
||||
g15836/in_0 +0 13998
|
||||
g15836/z (u) unmapped_not 1 4.2 0 +32 14030 F
|
||||
g15837/in_1 +0 14030
|
||||
g15837/z (u) unmapped_nand2 1 4.5 0 +41 14070 R
|
||||
g15838/in_1 +0 14070
|
||||
g15838/z (u) unmapped_nand2 1 4.2 0 +41 14111 F
|
||||
g15907/in_1 +0 14111
|
||||
g15907/z (u) unmapped_nand2 1 4.5 0 +41 14152 R
|
||||
g15908/in_1 +0 14152
|
||||
g15908/z (u) unmapped_nand2 1 4.2 0 +41 14193 F
|
||||
g15990/in_0 +0 14193
|
||||
g15990/z (u) unmapped_nand2 1 4.5 0 +41 14233 R
|
||||
g15991/in_1 +0 14233
|
||||
g15991/z (u) unmapped_nand2 1 4.2 0 +41 14274 F
|
||||
g15993/in_0 +0 14274
|
||||
g15993/z (u) unmapped_nand2 2 9.0 0 +51 14325 R
|
||||
g186/in_0 +0 14325
|
||||
g186/z (u) unmapped_and2 1 4.5 0 +41 14365 R
|
||||
g187/in_1 +0 14365
|
||||
g187/z (u) unmapped_or2 1 4.5 0 +41 14406 R
|
||||
Alu_3_div_202_57/QUOTIENT[0]
|
||||
g57705/data4 +0 14406
|
||||
g57705/z (u) unmapped_mux20 8 36.0 0 +168 14574 R
|
||||
RegisterFiles/io_inputs_3[0]
|
||||
g2841_g2967/data1 +0 14574
|
||||
g2841_g2967/z (u) unmapped_mux12 1 4.5 0 +120 14694 R
|
||||
regs_7_reg[0]/d <<< unmapped_d_flop +0 14694
|
||||
regs_7_reg[0]/clk setup 400 +56 14750 R
|
||||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
||||
(clock clk) capture 10000 R
|
||||
------------------------------------------------------------------------------------------------
|
||||
Timing slack : -4750ps (TIMING VIOLATION)
|
||||
Start-point : topModule/configController_cycleReg_reg[0]/clk
|
||||
End-point : topModule/RegisterFiles/regs_7_reg[0]/d
|
||||
|
||||
(u) : Net has unmapped pin(s).
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,34 @@
|
|||
import ops.syn as syn
|
||||
from cfg import Design
|
||||
import subprocess, os
|
||||
|
||||
class MyFlow(object):
|
||||
|
||||
def __init__(self):
|
||||
self.points = []
|
||||
self.ops = []
|
||||
|
||||
def excute(self, design):
|
||||
design_name = design.top_name
|
||||
make_file = open("Makefile", "w")
|
||||
self.ops[0].config(design_name + "_" + self.points[0])
|
||||
make_file.write("all:\n")
|
||||
make_file.write("\tgenus -legacy_ui -batch -files " + design_name + "_" + self.points[0] + ".tcl\n")
|
||||
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
|
||||
design = Design("TopModuleWrapper")
|
||||
|
||||
my_flow = MyFlow()
|
||||
op_synth = syn.GenusSynth(design)
|
||||
my_flow.ops.append(op_synth)
|
||||
my_flow.points.append("to_synth")
|
||||
|
||||
my_flow.excute(design)
|
||||
|
||||
cmd = 'make'
|
||||
|
||||
subprocess.Popen(cmd)
|
||||
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
class Params():
|
||||
def __init__(self, typ, name, value, optional = False):
|
||||
self.type = typ
|
||||
self.name = name
|
||||
self.range = []
|
||||
self.value = value
|
||||
self.optional = optional
|
||||
|
||||
def check_valid(self):
|
||||
return True
|
||||
|
||||
class GenusSynth():
|
||||
def __init__(self, design):
|
||||
self.params = dict()
|
||||
self.params["effort"] = "medium"
|
||||
self.params["is_incremental"] = True
|
||||
self.params["spatial"] = False
|
||||
self.design = design
|
||||
self.design.obj_hdl = design.obj_path + "/" + design.top_name + ".vh"
|
||||
self.design.obj_sdc = design.obj_path + "/" + design.top_name + "_synth.sdc"
|
||||
self.design.rpt_gates = design.rpt_path + "/" + "gates_synth.rpt"
|
||||
self.design.rpt_timing = design.rpt_path + "/" + "timing_synth.rpt"
|
||||
self.design.rpt_power = design.rpt_path + "/" + "power_synth.rpt"
|
||||
|
||||
def setParams(self, param, optional):
|
||||
if self.params.get(param) is not None:
|
||||
self.params[param] = optional
|
||||
else:
|
||||
assert False, 'Unknown param'
|
||||
|
||||
def config(self, tcl_file):
|
||||
tcl = open(tcl_file + ".tcl", 'w', encoding='utf-8')
|
||||
|
||||
tcl.write('set hdl_files %s\n'%(self.design.rtl_file))
|
||||
tcl.write('set DESIGN %s\n'%(self.design.top_name))
|
||||
tcl.write('set clkpin %s\n'%(self.design.clk_name))
|
||||
tcl.write('set delay %d\n'%(self.design.delay))
|
||||
tcl.write('set_attribute hdl_search_path %s\n'%(self.design.hdl_path))
|
||||
tcl.write('set_attribute lib_search_path %s\n'%(self.design.lib_path))
|
||||
tcl.write('set_attribute information_level 6 \n')
|
||||
tcl.write('set_attribute library %s\n'%(self.design.lib_file))
|
||||
tcl.write('read_hdl ${hdl_files} \n')
|
||||
tcl.write('elaborate $DESIGN \n')
|
||||
tcl.write('set clock [define_clock -period ${delay} -name ${clkpin} [clock_ports]]\n')
|
||||
tcl.write('external_delay -input 0 -clock clk [find / -port ports_in/*]\n')
|
||||
tcl.write('external_delay -output 0 -clock clk [find / -port ports_out/*]\n')
|
||||
tcl.write('dc::set_clock_transition .4 clk\n')
|
||||
tcl.write('check_design -unresolved\n')
|
||||
tcl.write('report timing -lint\n')
|
||||
|
||||
ret = 'synthesize'
|
||||
|
||||
for i in self.params:
|
||||
if self.params[i]:
|
||||
ret = ret + " -" + i
|
||||
|
||||
tcl.write(ret + '\n')
|
||||
|
||||
tcl.write("report timing > %s\n"%(self.design.rpt_timing))
|
||||
tcl.write('report gates > %s\n'%(self.design.rpt_gates))
|
||||
tcl.write('report power > %s\n'%(self.design.rpt_power))
|
||||
tcl.write('write_hdl -mapped > %s\n'%(self.design.obj_hdl))
|
||||
tcl.write('write_sdc > %s\n'%(self.design.obj_sdc))
|
||||
|
||||
tcl.close()
|
||||
|
||||
class Output(object):
|
||||
|
||||
def __init__(self, design):
|
||||
pass
|
||||
|
||||
def config(self, file_name):
|
||||
f = open(file_name + ".tcl", "w")
|
||||
# to-do
|
||||
f.close()
|
||||
|
||||
|
||||
Loading…
Reference in New Issue