169 lines
4.3 KiB
C
169 lines
4.3 KiB
C
/* Copyright 2018 Canaan Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _DRIVER_GPIO_H
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#define _DRIVER_GPIO_H
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#include "platform.h"
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#include <inttypes.h>
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#include <stddef.h>
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#include "gpio_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Structure for accessing GPIO registers by individual bit
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*/
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typedef struct _gpio_bits
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{
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uint32_t b0 : 1;
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uint32_t b1 : 1;
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uint32_t b2 : 1;
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uint32_t b3 : 1;
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uint32_t b4 : 1;
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uint32_t b5 : 1;
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uint32_t b6 : 1;
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uint32_t b7 : 1;
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uint32_t b8 : 1;
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uint32_t b9 : 1;
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uint32_t b10 : 1;
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uint32_t b11 : 1;
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uint32_t b12 : 1;
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uint32_t b13 : 1;
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uint32_t b14 : 1;
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uint32_t b15 : 1;
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uint32_t b16 : 1;
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uint32_t b17 : 1;
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uint32_t b18 : 1;
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uint32_t b19 : 1;
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uint32_t b20 : 1;
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uint32_t b21 : 1;
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uint32_t b22 : 1;
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uint32_t b23 : 1;
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uint32_t b24 : 1;
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uint32_t b25 : 1;
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uint32_t b26 : 1;
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uint32_t b27 : 1;
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uint32_t b28 : 1;
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uint32_t b29 : 1;
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uint32_t b30 : 1;
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uint32_t b31 : 1;
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} __attribute__((packed, aligned(4))) gpio_bits_t;
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/**
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* @brief Structure of templates for accessing GPIO registers
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*/
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typedef union _gpio_access_tp
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{
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/* 32x1 bit mode */
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uint32_t u32[1];
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/* 16x2 bit mode */
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uint16_t u16[2];
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/* 8x4 bit mode */
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uint8_t u8[4];
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/* 1 bit mode */
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gpio_bits_t bits;
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} __attribute__((packed, aligned(4))) gpio_access_tp_t;
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/**
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* @brief The GPIO address map
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*/
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typedef struct _gpio
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{
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/* Offset 0x00: Data (output) registers */
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gpio_access_tp_t data_output;
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/* Offset 0x04: Data direction registers */
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gpio_access_tp_t direction;
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/* Offset 0x08: Data source registers */
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gpio_access_tp_t source;
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/* Offset 0x10 - 0x2f: Unused registers, 9x4 bytes */
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uint32_t unused_0[9];
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/* Offset 0x30: Interrupt enable/disable registers */
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gpio_access_tp_t interrupt_enable;
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/* Offset 0x34: Interrupt mask registers */
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gpio_access_tp_t interrupt_mask;
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/* Offset 0x38: Interrupt level registers */
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gpio_access_tp_t interrupt_level;
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/* Offset 0x3c: Interrupt polarity registers */
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gpio_access_tp_t interrupt_polarity;
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/* Offset 0x40: Interrupt status registers */
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gpio_access_tp_t interrupt_status;
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/* Offset 0x44: Raw interrupt status registers */
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gpio_access_tp_t interrupt_status_raw;
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/* Offset 0x48: Interrupt debounce registers */
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gpio_access_tp_t interrupt_debounce;
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/* Offset 0x4c: Registers for clearing interrupts */
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gpio_access_tp_t interrupt_clear;
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/* Offset 0x50: External port (data input) registers */
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gpio_access_tp_t data_input;
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/* Offset 0x54 - 0x5f: Unused registers, 3x4 bytes */
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uint32_t unused_1[3];
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/* Offset 0x60: Sync level registers */
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gpio_access_tp_t sync_level;
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/* Offset 0x64: ID code */
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gpio_access_tp_t id_code;
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/* Offset 0x68: Interrupt both edge type */
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gpio_access_tp_t interrupt_bothedge;
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} __attribute__((packed, aligned(4))) gpio_t;
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/**
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* @brief Bus GPIO object instance
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*/
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extern volatile gpio_t *const gpio;
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/**
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* @brief Gpio initialize
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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int gpio_init(void);
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/**
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* @brief Set Gpio drive mode
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*
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* @param[in] pin Gpio pin
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* @param[in] mode Gpio pin drive mode
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*/
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void gpio_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode);
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/**
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* @brief Get Gpio pin value
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*
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* @param[in] pin Gpio pin
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* @return Pin value
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*
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* - GPIO_PV_Low Gpio pin low
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* - GPIO_PV_High Gpio pin high
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*/
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gpio_pin_value_t gpio_get_pin(uint8_t pin);
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/**
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* @brief Set Gpio pin value
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*
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* @param[in] pin Gpio pin
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* @param[in] value Gpio pin value
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*/
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void gpio_set_pin(uint8_t pin, gpio_pin_value_t value);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVER_GPIO_H */
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