362 lines
13 KiB
C
362 lines
13 KiB
C
/* Copyright 2018 Canaan Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <stddef.h>
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#include "i2c.h"
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#include "utils.h"
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#include "fpioa.h"
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#include "platform.h"
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#include "stdlib.h"
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#include "string.h"
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#include "sysctl.h"
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#include "bsp.h"
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typedef struct _i2c_slave_instance
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{
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uint32_t i2c_num;
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const i2c_slave_handler_t *slave_handler;
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} i2c_slave_instance_t;
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static i2c_slave_instance_t slave_instance[I2C_MAX_NUM];
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typedef struct _i2c_instance
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{
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i2c_device_number_t i2c_num;
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i2c_transfer_mode_t transfer_mode;
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dmac_channel_number_t dmac_channel;
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plic_instance_t i2c_int_instance;
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spinlock_t lock;
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} i2c_instance_t;
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static i2c_instance_t g_i2c_instance[3];
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volatile i2c_t* const i2c[3] =
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{
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(volatile i2c_t*)I2C0_BASE_ADDR,
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(volatile i2c_t*)I2C1_BASE_ADDR,
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(volatile i2c_t*)I2C2_BASE_ADDR
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};
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static void i2c_clk_init(i2c_device_number_t i2c_num)
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{
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configASSERT(i2c_num < I2C_MAX_NUM);
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sysctl_clock_enable(SYSCTL_CLOCK_I2C0 + i2c_num);
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sysctl_clock_set_threshold(SYSCTL_THRESHOLD_I2C0 + i2c_num, 3);
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}
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void i2c_init(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width,
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uint32_t i2c_clk)
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{
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configASSERT(i2c_num < I2C_MAX_NUM);
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configASSERT(address_width == 7 || address_width == 10);
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volatile i2c_t *i2c_adapter = i2c[i2c_num];
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i2c_clk_init(i2c_num);
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uint32_t v_i2c_freq = sysctl_clock_get_freq(SYSCTL_CLOCK_I2C0 + i2c_num);
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uint16_t v_period_clk_cnt = v_i2c_freq / i2c_clk / 2;
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if(v_period_clk_cnt == 0)
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v_period_clk_cnt = 1;
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i2c_adapter->enable = 0;
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i2c_adapter->con = I2C_CON_MASTER_MODE | I2C_CON_SLAVE_DISABLE | I2C_CON_RESTART_EN |
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(address_width == 10 ? I2C_CON_10BITADDR_SLAVE : 0) | I2C_CON_SPEED(1);
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i2c_adapter->ss_scl_hcnt = I2C_SS_SCL_HCNT_COUNT(v_period_clk_cnt);
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i2c_adapter->ss_scl_lcnt = I2C_SS_SCL_LCNT_COUNT(v_period_clk_cnt);
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i2c_adapter->tar = I2C_TAR_ADDRESS(slave_address);
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i2c_adapter->intr_mask = 0;
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i2c_adapter->dma_cr = 0x3;
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i2c_adapter->dma_rdlr = 0;
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i2c_adapter->dma_tdlr = 4;
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i2c_adapter->enable = I2C_ENABLE_ENABLE;
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}
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static int i2c_slave_irq(void *userdata)
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{
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i2c_slave_instance_t *instance = (i2c_slave_instance_t *)userdata;
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volatile i2c_t *i2c_adapter = i2c[instance->i2c_num];
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uint32_t status = i2c_adapter->intr_stat;
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if (status & I2C_INTR_STAT_START_DET)
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{
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instance->slave_handler->on_event(I2C_EV_START);
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readl(&i2c_adapter->clr_start_det);
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}
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if (status & I2C_INTR_STAT_STOP_DET)
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{
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instance->slave_handler->on_event(I2C_EV_STOP);
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readl(&i2c_adapter->clr_stop_det);
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}
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if (status & I2C_INTR_STAT_RX_FULL)
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{
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instance->slave_handler->on_receive(i2c_adapter->data_cmd);
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}
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if (status & I2C_INTR_STAT_RD_REQ)
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{
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i2c_adapter->data_cmd = instance->slave_handler->on_transmit();
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readl(&i2c_adapter->clr_rd_req);
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}
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return 0;
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}
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void i2c_init_as_slave(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width,
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const i2c_slave_handler_t *handler)
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{
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configASSERT(address_width == 7 || address_width == 10);
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volatile i2c_t *i2c_adapter = i2c[i2c_num];
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slave_instance[i2c_num].i2c_num = i2c_num;
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slave_instance[i2c_num].slave_handler = handler;
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i2c_clk_init(i2c_num);
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i2c_adapter->enable = 0;
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i2c_adapter->con = (address_width == 10 ? I2C_CON_10BITADDR_SLAVE : 0) | I2C_CON_SPEED(1) | I2C_CON_STOP_DET_IFADDRESSED;
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i2c_adapter->ss_scl_hcnt = I2C_SS_SCL_HCNT_COUNT(37);
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i2c_adapter->ss_scl_lcnt = I2C_SS_SCL_LCNT_COUNT(40);
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i2c_adapter->sar = I2C_SAR_ADDRESS(slave_address);
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i2c_adapter->rx_tl = I2C_RX_TL_VALUE(0);
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i2c_adapter->tx_tl = I2C_TX_TL_VALUE(0);
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i2c_adapter->intr_mask = I2C_INTR_MASK_RX_FULL | I2C_INTR_MASK_START_DET | I2C_INTR_MASK_STOP_DET | I2C_INTR_MASK_RD_REQ;
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plic_set_priority(IRQN_I2C0_INTERRUPT + i2c_num, 1);
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plic_irq_register(IRQN_I2C0_INTERRUPT + i2c_num, i2c_slave_irq, slave_instance + i2c_num);
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plic_irq_enable(IRQN_I2C0_INTERRUPT + i2c_num);
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i2c_adapter->enable = I2C_ENABLE_ENABLE;
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}
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int i2c_send_data(i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len)
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{
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configASSERT(i2c_num < I2C_MAX_NUM);
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volatile i2c_t* i2c_adapter = i2c[i2c_num];
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size_t fifo_len, index;
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i2c_adapter->clr_tx_abrt = i2c_adapter->clr_tx_abrt;
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while (send_buf_len)
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{
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fifo_len = 8 - i2c_adapter->txflr;
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fifo_len = send_buf_len < fifo_len ? send_buf_len : fifo_len;
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for (index = 0; index < fifo_len; index++)
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i2c_adapter->data_cmd = I2C_DATA_CMD_DATA(*send_buf++);
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if (i2c_adapter->tx_abrt_source != 0)
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return 1;
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send_buf_len -= fifo_len;
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}
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while ((i2c_adapter->status & I2C_STATUS_ACTIVITY) || !(i2c_adapter->status & I2C_STATUS_TFE))
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;
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if (i2c_adapter->tx_abrt_source != 0)
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return 1;
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return 0;
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}
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void i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_t i2c_num, const uint8_t *send_buf,
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size_t send_buf_len)
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{
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configASSERT(i2c_num < I2C_MAX_NUM);
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volatile i2c_t* i2c_adapter = i2c[i2c_num];
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i2c_adapter->clr_tx_abrt = i2c_adapter->clr_tx_abrt;
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uint32_t *buf = malloc(send_buf_len * sizeof(uint32_t));
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int i;
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for (i = 0; i < send_buf_len; i++)
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{
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buf[i] = send_buf[i];
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}
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sysctl_dma_select((sysctl_dma_channel_t)dma_channel_num, SYSCTL_DMA_SELECT_I2C0_TX_REQ + i2c_num * 2);
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dmac_set_single_mode(dma_channel_num, buf, (void *)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
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DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, send_buf_len);
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dmac_wait_done(dma_channel_num);
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free((void *)buf);
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while ((i2c_adapter->status & I2C_STATUS_ACTIVITY) || !(i2c_adapter->status & I2C_STATUS_TFE))
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{
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if (i2c_adapter->tx_abrt_source != 0)
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return;
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}
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}
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int i2c_recv_data(i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf,
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size_t receive_buf_len)
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{
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configASSERT(i2c_num < I2C_MAX_NUM);
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size_t fifo_len, index;
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size_t rx_len = receive_buf_len;
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volatile i2c_t* i2c_adapter = i2c[i2c_num];
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while (send_buf_len)
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{
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fifo_len = 8 - i2c_adapter->txflr;
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fifo_len = send_buf_len < fifo_len ? send_buf_len : fifo_len;
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for (index = 0; index < fifo_len; index++)
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i2c_adapter->data_cmd = I2C_DATA_CMD_DATA(*send_buf++);
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if (i2c_adapter->tx_abrt_source != 0)
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return 1;
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send_buf_len -= fifo_len;
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}
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while (receive_buf_len || rx_len)
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{
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fifo_len = i2c_adapter->rxflr;
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fifo_len = rx_len < fifo_len ? rx_len : fifo_len;
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for (index = 0; index < fifo_len; index++)
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*receive_buf++ = (uint8_t)i2c_adapter->data_cmd;
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rx_len -= fifo_len;
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fifo_len = 8 - i2c_adapter->txflr;
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fifo_len = receive_buf_len < fifo_len ? receive_buf_len : fifo_len;
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for (index = 0; index < fifo_len; index++)
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i2c_adapter->data_cmd = I2C_DATA_CMD_CMD;
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if (i2c_adapter->tx_abrt_source != 0)
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return 1;
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receive_buf_len -= fifo_len;
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}
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return 0;
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}
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void i2c_recv_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num,
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i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len,
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uint8_t *receive_buf, size_t receive_buf_len)
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{
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configASSERT(i2c_num < I2C_MAX_NUM);
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volatile i2c_t* i2c_adapter = i2c[i2c_num];
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uint32_t *write_cmd = malloc(sizeof(uint32_t) * (send_buf_len + receive_buf_len));
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size_t i;
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for(i = 0; i < send_buf_len; i++)
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write_cmd[i] = *send_buf++;
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for (i = 0; i < receive_buf_len; i++)
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write_cmd[i + send_buf_len] = I2C_DATA_CMD_CMD;
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sysctl_dma_select((sysctl_dma_channel_t)dma_send_channel_num, SYSCTL_DMA_SELECT_I2C0_TX_REQ + i2c_num * 2);
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sysctl_dma_select((sysctl_dma_channel_t)dma_receive_channel_num, SYSCTL_DMA_SELECT_I2C0_RX_REQ + i2c_num * 2);
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dmac_set_single_mode(dma_receive_channel_num, (void *)(&i2c_adapter->data_cmd), write_cmd, DMAC_ADDR_NOCHANGE,
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DMAC_ADDR_INCREMENT,DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, receive_buf_len);
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dmac_set_single_mode(dma_send_channel_num, write_cmd, (void *)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT,
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DMAC_ADDR_NOCHANGE,DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, receive_buf_len + send_buf_len);
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dmac_wait_done(dma_send_channel_num);
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dmac_wait_done(dma_receive_channel_num);
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for (i = 0; i < receive_buf_len; i++)
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{
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receive_buf[i] = (uint8_t)write_cmd[i];
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}
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free(write_cmd);
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}
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static int i2c_dma_irq(void *ctx)
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{
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i2c_instance_t *v_instance = (i2c_instance_t *)ctx;
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volatile i2c_t* i2c_adapter = i2c[v_instance->i2c_num];
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dmac_irq_unregister(v_instance->dmac_channel);
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if(v_instance->transfer_mode == I2C_SEND)
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{
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while ((i2c_adapter->status & I2C_STATUS_ACTIVITY) || !(i2c_adapter->status & I2C_STATUS_TFE))
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{
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if (i2c_adapter->tx_abrt_source != 0)
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{
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spinlock_unlock(&v_instance->lock);
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return -1;
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}
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}
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}
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spinlock_unlock(&v_instance->lock);
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if(v_instance->i2c_int_instance.callback)
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{
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v_instance->i2c_int_instance.callback(v_instance->i2c_int_instance.ctx);
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}
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return 0;
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}
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void i2c_handle_data_dma(i2c_device_number_t i2c_num, i2c_data_t data, plic_interrupt_t *cb)
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{
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configASSERT(i2c_num < I2C_MAX_NUM);
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configASSERT(data.tx_channel < DMAC_CHANNEL_MAX && data.rx_channel < DMAC_CHANNEL_MAX);
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spinlock_lock(&g_i2c_instance[i2c_num].lock);
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if(cb)
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{
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g_i2c_instance[i2c_num].i2c_int_instance.callback = cb->callback;
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g_i2c_instance[i2c_num].i2c_int_instance.ctx = cb->ctx;
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}
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volatile i2c_t* i2c_adapter = i2c[i2c_num];
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if(data.transfer_mode == I2C_SEND)
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{
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configASSERT(data.tx_buf && data.tx_len);
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i2c_adapter->clr_tx_abrt = i2c_adapter->clr_tx_abrt;
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if(cb)
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{
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g_i2c_instance[i2c_num].dmac_channel = data.tx_channel;
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g_i2c_instance[i2c_num].transfer_mode = I2C_SEND;
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dmac_irq_register(data.tx_channel, i2c_dma_irq, &g_i2c_instance[i2c_num], cb->priority);
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}
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sysctl_dma_select((sysctl_dma_channel_t)data.tx_channel, SYSCTL_DMA_SELECT_I2C0_TX_REQ + i2c_num * 2);
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dmac_set_single_mode(data.tx_channel, data.tx_buf, (void *)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
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DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, data.tx_len);
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if(!cb)
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{
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dmac_wait_done(data.tx_channel);
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while ((i2c_adapter->status & I2C_STATUS_ACTIVITY) || !(i2c_adapter->status & I2C_STATUS_TFE))
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{
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if (i2c_adapter->tx_abrt_source != 0)
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configASSERT(!"source abort");
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}
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}
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}
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else
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{
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configASSERT(data.rx_buf && data.rx_len);
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if(data.tx_len)
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configASSERT(data.tx_buf);
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if(cb)
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{
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g_i2c_instance[i2c_num].dmac_channel = data.rx_channel;
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g_i2c_instance[i2c_num].transfer_mode = I2C_RECEIVE;
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dmac_irq_register(data.rx_channel, i2c_dma_irq, &g_i2c_instance[i2c_num], cb->priority);
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}
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sysctl_dma_select((sysctl_dma_channel_t)data.rx_channel, SYSCTL_DMA_SELECT_I2C0_RX_REQ + i2c_num * 2);
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dmac_set_single_mode(data.rx_channel, (void *)(&i2c_adapter->data_cmd), data.rx_buf, DMAC_ADDR_NOCHANGE,
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DMAC_ADDR_INCREMENT,DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, data.rx_len);
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sysctl_dma_select((sysctl_dma_channel_t)data.tx_channel, SYSCTL_DMA_SELECT_I2C0_TX_REQ + i2c_num * 2);
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if(data.tx_len)
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{
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configASSERT(data.tx_buf);
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dmac_set_single_mode(data.tx_channel, data.tx_buf, (void *)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT,
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DMAC_ADDR_NOCHANGE,DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, data.tx_len);
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dmac_wait_done(data.tx_channel);
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}
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static uint32_t s_read_cmd = I2C_DATA_CMD_CMD;
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dmac_set_single_mode(data.tx_channel, &s_read_cmd, (void *)(&i2c_adapter->data_cmd), DMAC_ADDR_NOCHANGE,
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DMAC_ADDR_NOCHANGE,DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, data.rx_len);
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if(!cb)
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{
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dmac_wait_done(data.tx_channel);
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dmac_wait_done(data.rx_channel);
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}
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}
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if(!cb)
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spinlock_unlock(&g_i2c_instance[i2c_num].lock);
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}
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